中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.023 seconds)

    Nested Emulation And Dynamic Linking Environment
    2.
    发明申请
    Nested Emulation And Dynamic Linking Environment 审中-公开

    公开(公告)号：US20180173545A1

    公开(公告)日：2018-06-21

    申请号：US15843822

    申请日：2017-12-15

    Applicant: Intel Corporation

    Inventor： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Chen ,  Tingtao Li ,  Yong Wu ,  Wen Tan ,  Xiao Dong Lin

    IPC: G06F9/455 ,  G06F9/445

    CPC classification number: G06F9/455 ,  G06F9/44521 ,  G06F9/4552

    Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

    METHODS AND APPARATUS TO PROCESS A MACHINE LEARNING MODEL IN A WEB-BROWSER ENVIRONMENT
    3.
    发明申请
    METHODS AND APPARATUS TO PROCESS A MACHINE LEARNING MODEL IN A WEB-BROWSER ENVIRONMENT 有权

    公开(公告)号：US20220253488A1

    公开(公告)日：2022-08-11

    申请号：US17630461

    申请日：2019-09-27

    Applicant: Intel Corporation

    Inventor： Jianhui Li ,  Yong Wu ,  Ningxin Hu ,  Yiqiang Li ,  Yuanke Luo

    IPC: G06F16/954 ,  G06N3/04 ,  G06N3/08

    Abstract: Methods, apparatus, systems, and articles of manufacture to process a machine learning model in a web-browser environment are disclosed. An example apparatus includes a graph builder to accumulate machine learning operations as a graph. A tensor manager is to, in response to a request to access a tensor that is not yet available and associated with the machine learning operations, identify the graph based on the tensor. A graph cache manager is to determine whether a condensed graph corresponding to the identified graph is available. A graph condenser is to, in response to the graph cache manager determining that the condensed graph is not available, generate the condensed graph. A graph executor is to execute the condensed graph to create the tensor. The tensor manager is to provide the tensor as a response to the request to access the tensor.

    EFFICIENT ADDRESS TRANSLATION
    7.
    发明申请
    EFFICIENT ADDRESS TRANSLATION 有权

    公开(公告)号：US20220405210A1

    公开(公告)日：2022-12-22

    申请号：US17892879

    申请日：2022-08-22

    Applicant: Intel Corporation

    Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

    IPC: G06F12/10 ,  G06F9/455 ,  G06F9/355 ,  G06F9/30

    Abstract: An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

    Efficient address translation
    8.
    发明授权
    Efficient address translation 有权

    公开(公告)号：US12079138B2

    公开(公告)日：2024-09-03

    申请号：US17892879

    申请日：2022-08-22

    Applicant: Intel Corporation

    Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

    IPC: G06F12/10 ,  G06F9/30 ,  G06F9/355 ,  G06F9/455

    CPC classification number: G06F12/10 ,  G06F9/30174 ,  G06F9/355 ,  G06F9/45554 ,  G06F9/45558 ,  G06F2009/45583

    Abstract: An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

    OPTIMIZING LOW PRECISION INFERENCE MODELS FOR DEPLOYMENT OF DEEP NEURAL NETWORKS
    9.
    发明申请
    OPTIMIZING LOW PRECISION INFERENCE MODELS FOR DEPLOYMENT OF DEEP NEURAL NETWORKS 有权

    公开(公告)号：US20230118802A1

    公开(公告)日：2023-04-20

    申请号：US17929023

    申请日：2020-03-13

    Applicant: Intel Corporation

    Inventor： Jiong Gong ,  Yong Wu ,  Haihao Shen ,  Xiao Dong Lin ,  Guoming Zhang ,  Feng Yuan

    IPC: G06N3/0495 ,  G06N3/08

    Abstract: Systems, apparatuses and methods may provide technology for optimizing an inference neural network model that performs asymmetric quantization by generating a quantized neural network, wherein model weights of the neural network are quantized as signed integer values, and wherein an input layer of the neural network is configured to quantize input values as unsigned integer values, generating a weights accumulation table based on the quantized model weights and a kernel size for the neural network, and generating an output restoration function for an output layer of the neural network based on the weights accumulation table and the kernel size. The technology may also perform per-input channel quantization. The technology may also perform mixed-precision auto-tuning.

    Efficient address translation
    10.
    发明授权
    Efficient address translation 有权

    公开(公告)号：US11422943B2

    公开(公告)日：2022-08-23

    申请号：US15553853

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

    IPC: G06F12/10 ,  G06F9/455 ,  G06F9/355 ,  G06F9/30

    Abstract: One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

Patent Agency Ranking