中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.015 seconds)

    Nested Emulation And Dynamic Linking Environment
    1.
    发明申请
    Nested Emulation And Dynamic Linking Environment 审中-公开

    公开(公告)号：US20180173545A1

    公开(公告)日：2018-06-21

    申请号：US15843822

    申请日：2017-12-15

    Applicant: Intel Corporation

    Inventor： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Chen ,  Tingtao Li ,  Yong Wu ,  Wen Tan ,  Xiao Dong Lin

    IPC: G06F9/455 ,  G06F9/445

    CPC classification number: G06F9/455 ,  G06F9/44521 ,  G06F9/4552

    Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

    OPTIMIZING LOW PRECISION INFERENCE MODELS FOR DEPLOYMENT OF DEEP NEURAL NETWORKS
    4.
    发明申请
    OPTIMIZING LOW PRECISION INFERENCE MODELS FOR DEPLOYMENT OF DEEP NEURAL NETWORKS 有权

    公开(公告)号：US20230118802A1

    公开(公告)日：2023-04-20

    申请号：US17929023

    申请日：2020-03-13

    Applicant: Intel Corporation

    Inventor： Jiong Gong ,  Yong Wu ,  Haihao Shen ,  Xiao Dong Lin ,  Guoming Zhang ,  Feng Yuan

    IPC: G06N3/0495 ,  G06N3/08

    Abstract: Systems, apparatuses and methods may provide technology for optimizing an inference neural network model that performs asymmetric quantization by generating a quantized neural network, wherein model weights of the neural network are quantized as signed integer values, and wherein an input layer of the neural network is configured to quantize input values as unsigned integer values, generating a weights accumulation table based on the quantized model weights and a kernel size for the neural network, and generating an output restoration function for an output layer of the neural network based on the weights accumulation table and the kernel size. The technology may also perform per-input channel quantization. The technology may also perform mixed-precision auto-tuning.

    MULTIPLE PROCESSOR MODES EXECUTION METHOD AND APPARATUS INCLUDING SIGNAL HANDLING
    7.
    发明申请
    MULTIPLE PROCESSOR MODES EXECUTION METHOD AND APPARATUS INCLUDING SIGNAL HANDLING 有权
    多处理器模式执行方法和设备，包括信号处理

    公开(公告)号：US20160350161A1

    公开(公告)日：2016-12-01

    申请号：US14724394

    申请日：2015-05-28

    Applicant: Intel Corporation

    Inventor： Yihua Jin ,  Xiao Dong Lin ,  Yong Wu ,  Jianhui Li ,  Xueliang Zhong

    IPC: G06F9/54 ,  G06F12/08 ,  G06F9/46 ,  G06F12/02

    CPC classification number: G06F9/54 ,  G06F9/461 ,  G06F9/466 ,  G06F12/0284 ,  G06F12/0842 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/62

    Abstract: Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

    Abstract translation: 这里描述了与多个处理器模式执行相关联的装置，方法和存储介质。 在实施例中，装置可以包括具有多个处理器模式的处理器，包括用于寻址第一地址空间的第一处理器模式和用于寻址第二地址空间的第二处理器模式，所述第二地址空间包括第一地址空间。 该装置还可以包括处理来自内核的信号的信号处理器，处于第一处理器模式; 以及信号处理器包装器，用于在从内核传递信号时将处理器切换到第二处理器模式，将第二处理器模式的当前额外上下文从第二寄存器文件保存到用户堆栈，将处理器切换回第一 处理器模式，然后调用信号处理程序来处理信号。 可以描述或要求保护其他实施例。

    SCENARIO PROFILE BASED PARTITIONING AND MANAGEMENT OF APPLICATION CODE
    8.
    发明申请
    SCENARIO PROFILE BASED PARTITIONING AND MANAGEMENT OF APPLICATION CODE 有权

    公开(公告)号：US20210368023A1

    公开(公告)日：2021-11-25

    申请号：US16973856

    申请日：2019-01-17

    Applicant: INTEL CORPORATION

    Inventor： Shoumeng Yan ,  Xiao Dong Lin ,  Yao Zu Dong ,  Zhen Zhou ,  Bin Yang

    IPC: H04L29/08

    Abstract: Method, systems and apparatuses may provide for technology that divides an application into a plurality of portions that are each associated with one or more functions of the application and determine a plurality of transition probabilities between the plurality of portions. Some technology may also receive at least a first portion of the plurality of portions, and receive a relation file indicating the plurality of transition probabilities between the plurality of portions.

    Nested emulation and dynamic linking environment
    9.
    发明授权
    Nested emulation and dynamic linking environment 有权

    公开(公告)号：US10761867B2

    公开(公告)日：2020-09-01

    申请号：US15843822

    申请日：2017-12-15

    Applicant: Intel Corporation

    Inventor： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Chen ,  Tingtao Li ,  Yong Wu ,  Wen Tan ,  Xiao Dong Lin

    IPC: G06G7/48 ,  G06F9/455 ,  G06F9/445

    Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

Patent Agency Ranking