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公开(公告)号：US10854590B2
公开(公告)日：2020-12-01
申请号：US15776378
申请日：2015-12-23
申请人： Intel IP Corporation
IPC分类号： H01L23/02 , H01L25/00 , H01L25/065 , H05K1/11
摘要： An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.
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公开(公告)号：US10301176B2
公开(公告)日：2019-05-28
申请号：US15857461
申请日：2017-12-28
申请人： Intel IP Corporation
摘要： In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
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公开(公告)号：US10228725B2
公开(公告)日：2019-03-12
申请号：US15282633
申请日：2016-09-30
申请人： Intel IP Corporation
发明人： Sven Albers , Klaus Reingruber , Andreas Wolter , Georg Seidemann , Christian Geissler , Thorsten Meyer , Gerald Ofner
IPC分类号： A44C5/00 , A44C5/02 , A44C5/10 , A45F5/00 , A61B5/00 , A61B5/11 , G06F1/16 , A61B5/021 , A61B5/024 , G04B37/14 , G04B47/00 , A61B5/0205 , H04B1/3827
摘要： A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.
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公开(公告)号：US20180342431A1
公开(公告)日：2018-11-29
申请号：US15778410
申请日：2015-12-18
申请人： Intel IP Corporation
IPC分类号： H01L23/13 , H01L23/498
摘要： An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.
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公开(公告)号：US10522485B2
公开(公告)日：2019-12-31
申请号：US15776474
申请日：2015-12-21
申请人： Intel IP Corporation
发明人： Christian Geissler , Sven Albers , Georg Seidemann , Andreas Wolter , Klaus Reingruber , Thomas Wagner , Marc Dittes
IPC分类号： H01L23/52 , H01L23/00 , H01L21/768 , H01L23/525 , H01L23/532
摘要： An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.
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公开(公告)号：US10347558B2
公开(公告)日：2019-07-09
申请号：US15748475
申请日：2015-08-31
申请人： INTEL IP CORPORATION
IPC分类号： H01L23/00 , H01L25/065 , H01L23/367 , H01L25/04 , H01L25/07 , H01L23/13 , H01L23/36 , H01L23/42 , H01L21/56 , H01L23/498
摘要： Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.
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公开(公告)号：US20190072732A1
公开(公告)日：2019-03-07
申请号：US16182450
申请日：2018-11-06
申请人： Intel IP Corporation
发明人： Georg Seidemann , Christian Geissler , Sven Albers , Thomas Wagner , Marc Dittes , Klaus Reingruber , Andreas Wolter , Richard Patten
CPC分类号： G02B6/428 , G02B6/12002 , G02B6/122 , G02B6/1221 , G02B6/132 , G02B6/30 , G02B6/4232 , G02B6/4238 , G02B6/43 , G02B2006/12197
摘要： Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
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公开(公告)号：US10209466B2
公开(公告)日：2019-02-19
申请号：US15089524
申请日：2016-04-02
申请人： Intel IP Corporation
发明人： Georg Seidemann , Christian Geissler , Sven Albers , Thomas Wagner , Marc Dittes , Klaus Reingruber , Andreas Wolter , Richard Patten
摘要： Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
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公开(公告)号：US10150668B2
公开(公告)日：2018-12-11
申请号：US15484765
申请日：2017-04-11
申请人： Intel IP Corporation
摘要： In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.
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公开(公告)号：US20180068939A1
公开(公告)日：2018-03-08
申请号：US15677835
申请日：2017-08-15
申请人： Intel IP Corporation
IPC分类号： H01L23/498 , H01L21/48
摘要： Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.
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