公开(公告)号：US20140124860A1

公开(公告)日：2014-05-08

申请号：US13670768

申请日：2012-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORP

Inventor： Kangguo Cheng ,  Veeraraghavan S. Basker ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins.

Abstract translation: 公开了用于形成局部绝缘体上硅（SOI）finFET的方法和结构。 翅片形成在块状基底上。 氮化物间隔件保护翅片侧壁。 浅沟槽隔离区域沉积在鳍片上。 氧化过程导致氧气扩散通过浅沟槽隔离区域并进入下面的硅。 氧与硅反应形成氧化物，为散热片提供电气隔离。 浅沟槽隔离区域与布置在鳍片上的翅片和/或氮化物间隔物直接物理接触。

公开(公告)号：US20140084249A1

公开(公告)日：2014-03-27

申请号：US13658007

申请日：2012-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORP

Inventor： Veeraraghavan S. Basker ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/775 ,  B82Y99/00

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439

Abstract: A nanowire field effect transistor device includes a first nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, and a second nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a plane, the plane arranged substantially orthogonal to a plane defined by a planar surface of the substrate.

Abstract translation: 纳米线场效应晶体管器件包括第一纳米线，其具有连接到源极区的第一远端，连接到漏极区的第二远端及其间的沟道区，布置在基底上的源极区和漏极区，以及 第二纳米线具有连接到源极区域的第一远端和连接到漏极区域的第二远端，以及其间的沟道区域，第一纳米线的纵向轴线和限定平面的第二纳米线的纵向轴线， 平面布置成基本上垂直于由衬底的平面表面限定的平面。

公开(公告)号：US20140103435A1

公开(公告)日：2014-04-17

申请号：US13650176

申请日：2012-10-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORP

Inventor： Veeraraghavan S. Basker ,  Effendi Leobandung ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: Fin-defining mask structures are formed over a semiconductor material layer. A semiconductor material portion is formed by patterning the semiconductor material layer, and a disposable gate structure is formed over the fin-defining mask structures. After formation of a disposable template layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed by etching center portions of the semiconductor material portion employing the combination of the disposable template layer and the fin-defining mask structures as an etch mask. A first pad region and a second pad region laterally contact the plurality of semiconductor fins. A replacement gate structure is formed on the plurality of semiconductor fins. The disposable template layer is removed, and the first pad region and the second pad regions are vertically recessed. Vertical source/drain junctions can be formed by introducing dopants through vertical sidewalls of the recessed source and second pad regions.

Abstract translation: 鳍形限定掩模结构形成在半导体材料层上。 通过图案化半导体材料层形成半导体材料部分，并且在鳍片限定掩模结构之上形成一次性栅极结构。 在形成一次性模板层之后，去除一次性栅极结构。 通过使用一次性模板层和鳍状限定掩模结构的组合蚀刻半导体材料部分的中心部分作为蚀刻掩模来形成多个半导体鳍片。 第一焊盘区域和第二焊盘区域横向接触多个半导体散热片。 在多个半导体鳍片上形成替换栅极结构。 去除一次性模板层，并且第一焊盘区域和第二焊盘区域是垂直凹进的。 可以通过将凹陷源和第二焊盘区域的垂直侧壁引入掺杂剂来形成垂直的源极/漏极结。