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公开(公告)号：US20230101678A1
公开(公告)日：2023-03-30
申请号：US17485088
申请日：2021-09-24
发明人： Albert Chu , Junli Wang , Brent Anderson
IPC分类号： G06F30/392
摘要： Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.
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公开(公告)号：US10742218B2
公开(公告)日：2020-08-11
申请号：US16042927
申请日：2018-07-23
发明人： Brent A. Anderson , Albert Chu
IPC分类号： H03K19/20 , H01L27/118 , H03K19/0948
摘要： A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.
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公开(公告)号：US20200028513A1
公开(公告)日：2020-01-23
申请号：US16042927
申请日：2018-07-23
发明人： Brent A. Anderson , Albert Chu
IPC分类号： H03K19/20 , H03K19/0948 , H01L27/118
摘要： A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.
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4.发明申请公开(公告)号：US20190206725A1
公开(公告)日：2019-07-04
申请号：US15859675
申请日：2018-01-01
发明人： Albert Chu , Kafai Lai , Lawrence A. Clevenger
IPC分类号： H01L21/768 , H01L23/498
摘要： Multi-patterning methods are provided for use in fabricating an array of metal lines comprising metal lines with different widths. For example, patterning methods implement spacer-is-dielectric (SID)-based self-aligned double patterning (SADP) methods for fabricating an array of metal lines comprising elongated metal lines with different widths, wherein an “unblock” mask is utilized as part of the process flow to overlap mandrel assigned and non-mandrel assigned features in a given SADP pattern to define regions to unblock a metal fill (remove dielectric material between wires) in a dielectric layer between defined metal lines of an a SADP pattern thus enabling the formation of wide metal lines within any region of a pattern of elongated metal lines formed with a minimum feature width.
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公开(公告)号：US20230307453A1
公开(公告)日：2023-09-28
申请号：US17701015
申请日：2022-03-22
发明人： Brent A Anderson , Junli Wang , Albert Chu
IPC分类号： H01L27/092 , H01L29/06 , H01L29/10 , H01L21/8238
CPC分类号： H01L27/0922 , H01L29/0665 , H01L29/1029 , H01L21/823807 , H01L21/823871
摘要： A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (Weff) Z, then the second logic cell has a height 2X, a width Y, and Weff>2.5 Z.
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公开(公告)号：US20230207553A1
公开(公告)日：2023-06-29
申请号：US17562331
申请日：2021-12-27
发明人： Ruilong Xie , Kisik Choi , Somnath Ghosh , Sagarika Mukesh , Albert Chu , Albert M. Young , Balasubramanian S. Pranatharthiharan , Huiming Bu , Kai Zhao , John Christopher Arnold , Brent A. Anderson , Dechao Guo
IPC分类号： H01L27/02 , H01L29/423 , H01L29/06 , H01L27/092 , H01L27/12 , H01L21/8234 , H01L21/762
CPC分类号： H01L27/0207 , H01L29/42392 , H01L29/0673 , H01L27/092 , H01L27/1251 , H01L21/823475 , H01L21/76229
摘要： A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.
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公开(公告)号：US20230178619A1
公开(公告)日：2023-06-08
申请号：US17541894
申请日：2021-12-03
发明人： Albert Chu , Junli Wang , Albert M. Young , Vidhi Zalani , Dechao Guo
IPC分类号： H01L29/423 , H01L27/088 , H01L29/786 , H01L21/8234 , H01L29/06
CPC分类号： H01L29/42392 , H01L21/823412 , H01L27/088 , H01L29/0665 , H01L29/78696
摘要： A semiconductor structure includes a first transistor device comprising a plurality of channel regions. The semiconductor structure further includes a second transistor device comprising a plurality of channel regions. The first transistor device and the second transistor device are disposed in a stacked configuration. The plurality of channel regions of the first transistor device are disposed in a staggered configuration relative to the plurality of channel regions of the second transistor device.
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公开(公告)号：US10832971B2
公开(公告)日：2020-11-10
申请号：US16117258
申请日：2018-08-30
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/092 , H01L21/3213 , H01L21/308
摘要： A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.
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9.发明授权公开(公告)号：US10755969B2
公开(公告)日：2020-08-25
申请号：US15859675
申请日：2018-01-01
发明人： Albert Chu , Kafai Lai , Lawrence A. Clevenger
IPC分类号： H01L21/768 , H01L23/498
摘要： Multi-patterning methods are provided for use in fabricating an array of metal lines comprising metal lines with different widths. For example, patterning methods implement spacer-is-dielectric (SID)-based self-aligned double patterning (SADP) methods for fabricating an array of metal lines comprising elongated metal lines with different widths, wherein an “unblock” mask is utilized as part of the process flow to overlap mandrel assigned and non-mandrel assigned features in a given SADP pattern to define regions to unblock a metal fill (remove dielectric material between wires) in a dielectric layer between defined metal lines of an a SADP pattern thus enabling the formation of wide metal lines within any region of a pattern of elongated metal lines formed with a minimum feature width.
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公开(公告)号：US12001772B2
公开(公告)日：2024-06-04
申请号：US17485088
申请日：2021-09-24
发明人： Albert Chu , Junli Wang , Brent Anderson
IPC分类号： G06F30/30 , G06F30/392 , H01L27/02 , G06F111/20
CPC分类号： G06F30/392 , H01L27/0207 , G06F2111/20
摘要： Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.
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