公开(公告)号：US20230101678A1

公开(公告)日：2023-03-30

申请号：US17485088

申请日：2021-09-24

申请人： International Business Machines Corporation

发明人： Albert Chu ,  Junli Wang ,  Brent Anderson

IPC分类号： G06F30/392

摘要： Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.

公开(公告)号：US10742218B2

公开(公告)日：2020-08-11

申请号：US16042927

申请日：2018-07-23

申请人： International Business Machines Corporation

发明人： Brent A. Anderson ,  Albert Chu

IPC分类号： H03K19/20 ,  H01L27/118 ,  H03K19/0948

摘要： A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.

公开(公告)号：US20200028513A1

公开(公告)日：2020-01-23

申请号：US16042927

申请日：2018-07-23

申请人： International Business Machines Corporation

发明人： Brent A. Anderson ,  Albert Chu

IPC分类号： H03K19/20 ,  H03K19/0948 ,  H01L27/118

摘要： A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.

公开(公告)号：US20190206725A1

公开(公告)日：2019-07-04

申请号：US15859675

申请日：2018-01-01

申请人： International Business Machines Corporation

发明人： Albert Chu ,  Kafai Lai ,  Lawrence A. Clevenger

IPC分类号： H01L21/768 ,  H01L23/498

摘要： Multi-patterning methods are provided for use in fabricating an array of metal lines comprising metal lines with different widths. For example, patterning methods implement spacer-is-dielectric (SID)-based self-aligned double patterning (SADP) methods for fabricating an array of metal lines comprising elongated metal lines with different widths, wherein an “unblock” mask is utilized as part of the process flow to overlap mandrel assigned and non-mandrel assigned features in a given SADP pattern to define regions to unblock a metal fill (remove dielectric material between wires) in a dielectric layer between defined metal lines of an a SADP pattern thus enabling the formation of wide metal lines within any region of a pattern of elongated metal lines formed with a minimum feature width.

公开(公告)号：US10832971B2

公开(公告)日：2020-11-10

申请号：US16117258

申请日：2018-08-30

申请人： International Business Machines Corporation

发明人： Rajasekhar Venigalla ,  Ravikumar Ramachandran ,  Albert Chu ,  Alan Thomas ,  Kafai Lai

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/308

摘要： A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate cut mask having one cut window exposing one or more portions of multiple sacrificial gate structures of the at least one plurality of sacrificial gate structures. The multiple sacrificial gate structures having been formed over portions of in structures. The method comprises forming a gate cut mask a plurality of semiconductor fins and a plurality of sacrificial gate structures. The gate cut mask being formed with one cut window exposing one or more portions of multiple sacrificial gate structures of the plurality of sacrificial gate structures. At least the portion of multiple sacrificial gate structures and one or more portions of each semiconductor fin of the plurality of semiconductor fins underlying the one or more portions of one of the multiple sacrificial gate structures are removed.

公开(公告)号：US10755969B2

公开(公告)日：2020-08-25

申请号：US15859675

申请日：2018-01-01

申请人： International Business Machines Corporation

发明人： Albert Chu ,  Kafai Lai ,  Lawrence A. Clevenger

IPC分类号： H01L21/768 ,  H01L23/498

摘要： Multi-patterning methods are provided for use in fabricating an array of metal lines comprising metal lines with different widths. For example, patterning methods implement spacer-is-dielectric (SID)-based self-aligned double patterning (SADP) methods for fabricating an array of metal lines comprising elongated metal lines with different widths, wherein an “unblock” mask is utilized as part of the process flow to overlap mandrel assigned and non-mandrel assigned features in a given SADP pattern to define regions to unblock a metal fill (remove dielectric material between wires) in a dielectric layer between defined metal lines of an a SADP pattern thus enabling the formation of wide metal lines within any region of a pattern of elongated metal lines formed with a minimum feature width.

公开(公告)号：US20220285259A1

公开(公告)日：2022-09-08

申请号：US17189528

申请日：2021-03-02

申请人： International Business Machines Corporation

发明人： Junli Wang ,  Albert Chu ,  Dechao Guo ,  Brent Anderson

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8238

摘要： A semiconductor structure comprises a front-end-of-line region comprising two or more devices, a first back-end-of-line region on a first side of the front-end-of-line region, the first back-end-of-line region comprising a first set of interconnects for at least a first subset of the two or more devices in the front-end-of-line region, and a second back-end-of-line region on a second side of the front-end-of-line region opposite the first side of the front-end-of-line region, the second back-end-of-line region comprising a second set of interconnects for at least a second subset of the two or more devices in the front-end-of-line region. The semiconductor structure also comprises one or more passthrough vias disposed in the front-end-of-line region, each of the one or more passthrough vias connecting at least one of the first set of interconnects of the first back-end-of-line region to at least one of the second set of interconnects of the second back-end-of-line region.

公开(公告)号：US11355401B1

公开(公告)日：2022-06-07

申请号：US17173356

申请日：2021-02-11

申请人： International Business Machines Corporation

发明人： Effendi Leobandung ,  Veeraraghavan S. Basker ,  Junli Wang ,  Albert Chu

IPC分类号： H01L21/8238 ,  H01L27/092

摘要： A method of forming a field effect transistor (FET) includes providing a substrate; forming an nFET source/drain region on the substrate; forming a pFET source/drain region on the substrate and adjacent to the nFET region, the nFET source/drain region directly contacting the pFET source/drain region; forming a first insulator layer on the nFET source/drain region and the pFET source/drain region; etching away a portion of the first insulator layer between the nFET source/drain region and the pFET source/drain region down to a level of the substrate, thereby breaking the contact between the nFET source/drain region and the pFET source/drain region; and forming a second insulator layer between the nFET source/drain region and the pFET source/drain region in a space formed by the etching, the second insulator layer extending from the substrate to a top of the first insulator layer. The second insulator layer is harder than the first insulator layer.