中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.015 seconds)

    Mitigating busy time in a high performance cache
    2.
    发明授权
    Mitigating busy time in a high performance cache 有权
    缓解高性能缓存中的繁忙时间

    公开(公告)号：US09158694B2

    公开(公告)日：2015-10-13

    申请号：US13664736

    申请日：2012-10-31

    Applicant: International Business Machines Corporation

    Inventor： Deanna P. Berger ,  Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diana L. Orf ,  Robert J. Sonnelitter, III

    IPC: G06F12/08

    CPC classification number: G06F12/0857 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F2212/1024 ,  G06F2212/281

    Abstract: A method, information processing device, and computer program product mitigate busy time in a hierarchical store-through memory cache structure. A cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

    Abstract translation: 一种方法，信息处理设备和计算机程序产品减轻分层存储到存储器高速缓存结构中的忙时间。 与存储器高速缓存相关联的高速缓存目录被分成多个部分，每个部分与部分存储器高速缓存相关联。 支持高速缓存目录的多个部分之间的同时高速缓存查找操作和缓存写入操作。 在通信地耦合到高速缓存目录的多个部分的共享高速缓存管道中同时处理两个或更多个存储命令。

    REDUCING PENALTIES FOR CACHE ACCESSING OPERATIONS
    3.
    发明申请
    REDUCING PENALTIES FOR CACHE ACCESSING OPERATIONS 有权
    减少高速缓存接入操作的处罚

    公开(公告)号：US20140095795A1

    公开(公告)日：2014-04-03

    申请号：US14095385

    申请日：2013-12-03

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

    IPC: G06F12/08

    CPC classification number: G06F12/0864 ,  G06F9/3824 ,  G06F12/0846 ,  G06F12/0855 ,  Y02D10/13

    Abstract: A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

    Abstract translation: 提供了用于减少高速缓存访​​问操作的惩罚的计算机程序产品。 计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。 该方法包括分别将平台寄存器与高速缓存阵列相关联，将控制信息和关于一个或多个高速缓存阵列执行的存储操作的数据加载到分别与一个或多个缓存阵列中的一个或多个 缓存阵列，并且基于一个或多个缓存阵列变得可用，使用来自相同平台寄存器的控制信息将一个或多个平台寄存器中的数据提交到一个或多个缓存阵列。

    Collecting failure information on error correction code (ECC) protected data
    4.
    发明授权
    Collecting failure information on error correction code (ECC) protected data 有权
    收集有关纠错码（ECC）保护数据的故障信息

    公开(公告)号：US08423875B2

    公开(公告)日：2013-04-16

    申请号：US13648555

    申请日：2012-10-10

    Applicant: International Business Machines Corporation

    Inventor： Arthur J. O'Neill ,  Patrick J. Meaney

    IPC: H03M13/00 ,  G11C29/00

    CPC classification number: G06F11/10

    Abstract: Methods and apparatus for error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.

    Abstract translation: 用于纠错码（ECC）调试的方法和装置可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。 该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。 该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

    Reducing penalties for cache accessing operations
    8.
    发明授权
    Reducing penalties for cache accessing operations 有权
    减少缓存访问操作的处罚

    公开(公告)号：US09047199B2

    公开(公告)日：2015-06-02

    申请号：US14095385

    申请日：2013-12-03

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Michael F. Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diane L. Orf

    IPC: G06F12/08 ,  G06F9/38

    CPC classification number: G06F12/0864 ,  G06F9/3824 ,  G06F12/0846 ,  G06F12/0855 ,  Y02D10/13

    Abstract: A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

    Abstract translation: 提供了用于减少高速缓存访​​问操作的惩罚的计算机程序产品。 计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。 该方法包括分别将平台寄存器与高速缓存阵列相关联，将控制信息和关于一个或多个高速缓存阵列执行的存储操作的数据加载到分别与一个或多个缓存阵列中的一个或多个 缓存阵列，并且基于一个或多个缓存阵列变得可用，使用来自相同平台寄存器的控制信息将一个或多个平台寄存器中的数据提交到一个或多个缓存阵列。

    MONITORING PROCESSING TIME IN A SHARED PIPELINE
    9.
    发明申请
    MONITORING PROCESSING TIME IN A SHARED PIPELINE 有权
    在共享管道中监控处理时间

    公开(公告)号：US20140095839A1

    公开(公告)日：2014-04-03

    申请号：US14095393

    申请日：2013-12-03

    Applicant: International Business Machines Corporation

    Inventor： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Christine C. Jones ,  Arthur J. O'Neill ,  Diana Lynn Orf ,  Robert J. Sonnelitter

    IPC: G06F9/38

    CPC classification number: G06F9/3867 ,  G06F11/3419 ,  G06F11/3466 ,  G06F2201/88

    Abstract: A pipelined processing device includes: a pipeline controller configured to receive at least one instruction associated with an operation from each of a plurality of subcontrollers, and input the at least one instruction into a pipeline; and a pipeline counter configured to receive an active time value from each of the plurality of subcontrollers, the active time value indicating at least a portion of a time taken to process the at least one instruction, the pipeline controller configured to route the active time value to a shared pipeline storage for performance analysis.

    Abstract translation: 流水线处理装置包括：流水线控制器，被配置为从多个子控制器中的每一个接收与操作相关联的至少一个指令，并将所述至少一个指令输入到流水线中; 以及流水线计数器，被配置为从所述多个子控制器中的每一个接收活动时间值，所述活动时间值指示处理所述至少一个指令所花费的时间的至少一部分，所述流水线控制器被配置为将所述活动时间值 到共享流水线存储进行性能分析。

    BITLINE DELETION
    10.
    发明申请
    BITLINE DELETION 有权

    公开(公告)号：US20130339809A1

    公开(公告)日：2013-12-19

    申请号：US13788744

    申请日：2013-03-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

    IPC: G06F11/08

    CPC classification number: G06F11/1064 ,  G06F11/073 ,  G06F11/076 ,  G06F11/08 ,  G11C2029/1204

    Abstract: Embodiments relate to a computer system for bitline deletion, the system including a cache controller and cache. The system is configured to perform a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line, recording a second address of the second error, comparing first and second bitline addresses, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to the third bitline address and deleting a location corresponding to the third cache line based on the activated bitline delete mode and matching third and second bitline addresses.

    Abstract translation: 实施例涉及用于位线删除的计算机系统，该系统包括高速缓存控制器和高速缓存。 该系统被配置为执行一种方法，包括当读取第一高速缓存线时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误，记录第二错误的第二地址，比较 第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三高速缓存线时检测第三错误，记录第三位线地址 将第二位线地址与第三位线地址进行比较，并且基于激活的位线删​​除模式和匹配的第三和第二位线地址来删除与第三高速缓存线对应的位置。

Patent Agency Ranking