公开(公告)号：US09250816B2

公开(公告)日：2016-02-02

申请号：US14013485

申请日：2013-08-29

Applicant: International Business Machines Corporation

Inventor： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0688 ,  G11C16/28 ,  G11C16/349

Abstract: A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

公开(公告)号：US20150347054A1

公开(公告)日：2015-12-03

申请号：US14826305

申请日：2015-08-14

Applicant: International Business Machines Corporation

Inventor： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0631 ,  G06F3/0653 ,  G06F3/0679 ,  G06F9/5016 ,  G06F12/02 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

Abstract: A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.

Abstract translation: 一种存储系统，包括内存系统和减少内存系统功耗的方法。 存储器系统包括可分配到多个处理器单元之一（例如处理器或处理器核）中的多个存储器单元。 存储器控制器从处理器单元接收对存储器的请求，并从存储器向每个请求处理器单元分配足够的空间。 分配的存储器可以包括存储每个单元的单个位的单个单元（SLC）存储器单元和存储每个单元多于一个位的其它存储器单元。 因此，两个处理器单元可以被分配相同的存储器空间，而一个或更少个分配给另一个的单元的数量。

公开(公告)号：US20140281294A1

公开(公告)日：2014-09-18

申请号：US13842375

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0688 ,  G11C16/28 ,  G11C16/349

Abstract: A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

Abstract translation: 在存储器件中采用磨损均衡技术，使得存储器块的循环历史由代表性存储器单元或少量代表性存储器单元的循环历史来表示。 控制逻辑块跟踪一个或多个代表性存储器单元的循环历史。 在存储器件内提供了表示用于感测电路的参考变量的最佳值的预测偏移作为循环历史的函数的表格。 在感测存储器单元之前，控制逻辑块检查一个或多个代表性存储器单元中的循环总数，并调整感测电路中参考变量的值，从而为感测中的参考变量提供最佳值 电路用于存储器件的每个感测周期。

公开(公告)号：US20140281162A1

公开(公告)日：2014-09-18

申请号：US14013485

申请日：2013-08-29

Applicant: International Business Machines Corporation

Inventor： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0688 ,  G11C16/28 ,  G11C16/349

Abstract: A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

公开(公告)号：US09311009B2

公开(公告)日：2016-04-12

申请号：US14826305

申请日：2015-08-14

Applicant: International Business Machines Corporation

Inventor： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F3/0625 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0631 ,  G06F3/0653 ,  G06F3/0679 ,  G06F9/5016 ,  G06F12/02 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

Abstract: A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.

Abstract translation: 一种存储系统，包括内存系统和减少内存系统功耗的方法。 存储器系统包括可分配到多个处理器单元之一（例如处理器或处理器核）中的多个存储器单元。 存储器控制器从处理器单元接收对存储器的请求，并从存储器向每个请求处理器单元分配足够的空间。 分配的存储器可以包括存储每个单元的单个位的单个单元（SLC）存储器单元和存储每个单元多于一个位的其它存储器单元。 因此，两个处理器单元可以被分配相同的存储器空间，而一个或更少个分配给另一个的单元的数量。

公开(公告)号：US09122404B2

公开(公告)日：2015-09-01

申请号：US13842375

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0688 ,  G11C16/28 ,  G11C16/349

Abstract: A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

Abstract translation: 在存储器件中采用磨损均衡技术，使得存储器块的循环历史由代表性存储器单元或少量代表性存储器单元的循环历史来表示。 控制逻辑块跟踪一个或多个代表性存储器单元的循环历史。 在存储器件内提供了表示用于感测电路的参考变量的最佳值的预测偏移作为循环历史的函数的表格。 在感测存储器单元之前，控制逻辑块检查一个或多个代表性存储器单元中的循环总数，并调整感测电路中参考变量的值，从而为感测中的参考变量提供最佳值 电路用于存储器件的每个感测周期。