公开(公告)号：US20190187995A1

公开(公告)日：2019-06-20

申请号：US15844998

申请日：2017-12-18

Applicant: International Business Machines Corporation

Inventor： David R. TERRY ,  Dung Q. NGUYEN ,  Brian W. THOMPTO ,  Joshua W. BOWMAN ,  Steven J. BATTLE ,  Brian D. BARRICK ,  Sundeep CHADHA ,  Albert J. VAN NORSTRAND, JR.

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3859 ,  G06F9/30105 ,  G06F9/30127 ,  G06F9/30145 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3851

Abstract: Techniques are disclosed for performing a flush and restore of a history buffer (HB) in a processing unit. One technique inludes identifying one or more entries of the HB to restore to a register file in the processing unit. For each of the one or more HB entries, a determination is made whether to send the HB entry to the register file via a first restore bus or via a second restore bus, different from the first restore bus, based on contents of the HB entry. Each of the one or more HB entries is then sent to the register file via one of the first restore bus or the second restore bus, based on the determination.

公开(公告)号：US20170351568A1

公开(公告)日：2017-12-07

申请号：US15173091

申请日：2016-06-03

Applicant: International Business Machines Corporation

Inventor： Brian D. BARRICK ,  James W. BISHOP ,  Maarten J. BOERSMA ,  Marcy E. BYERS ,  Sundeep CHADHA ,  Jentje LEENSTRA ,  Dung Q. NGUYEN ,  David R. TERRY

IPC: G06F11/10 ,  G06F9/38 ,  G06F9/30 ,  G11C29/52

CPC classification number: G06F11/106 ,  G06F9/30098 ,  G06F9/3016 ,  G06F9/3855 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data and error correcting code data to an execution unit, where the first data and error correcting code data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.

公开(公告)号：US20170003969A1

公开(公告)日：2017-01-05

申请号：US14755570

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Salma AYUB ,  Josh BOWMAN ,  Sundeep CHADHA ,  Dhivya JEGANATHAN ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F1/10 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851

Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.

公开(公告)号：US20160371091A1

公开(公告)日：2016-12-22

申请号：US14742427

申请日：2015-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey C. BROWNSCHEIDLE ,  Sundeep CHADHA ,  Maureen A. DELANEY ,  Dung Q. NGUYEN

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3855

Abstract: Techniques are disclosed for issuing instructions in a processor. According to one embodiment of the present disclosure, an instruction tag is broadcast to wake up a plurality of instructions stored in an issue queue that are dependent on an issued instruction associated with the instruction tag. Each of the plurality of instructions has an execution latency. One or more of the instructions having an execution that will collide with an execution of one of the issued instructions if issued in a next clock cycle are identified based on the execution latencies. The identified one or more instructions are delayed from issue by at least one clock cycle after the next clock cycle.

公开(公告)号：US20190188133A1

公开(公告)日：2019-06-20

申请号：US15845757

申请日：2017-12-18

Applicant: International Business Machines Corporation

Inventor： David R. TERRY ,  Dung Q. NGUYEN ,  Brian W. THOMPTO ,  Joshua W. BOWMAN ,  Steven J. BATTLE ,  Sundeep CHADHA ,  Brian D. BARRICK ,  Albert J. VAN NORSTRAND, JR.

IPC: G06F12/0804

CPC classification number: G06F12/0804 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.

公开(公告)号：US20180336108A1

公开(公告)日：2018-11-22

申请号：US15596818

申请日：2017-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steven J. BATTLE ,  Joshua W. BOWMAN ,  Sundeep CHADHA ,  Dhivya JEGANATHAN ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN ,  Tu-An T. NGUYEN ,  David R. TERRY

IPC: G06F11/16 ,  G06F11/20 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments include systems, methods, and computer program products for on-demand error detection and correction of registers in a processor. One method includes detecting, before a first instruction is dispatched to an issue queue in the processor, an error in data, associated with the first instruction, stored in an entry of a register file in the processor. The method also includes, after detecting the error, halting the dispatch of the first instruction to the issue queue, and determining whether the entry of the register file has completed. The method further includes determining whether to perform error correction on the register file based on the determination of whether the entry of the register file has completed.

公开(公告)号：US20170168818A1

公开(公告)日：2017-06-15

申请号：US15044412

申请日：2016-02-16

Applicant: International Business Machines Corporation

Inventor： Salma AYUB ,  Brian D. BARRICK ,  Joshua W. BOWMAN ,  Sundeep CHADHA ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN ,  David R. TERRY ,  Jing ZHANG

IPC: G06F9/30

CPC classification number: G06F9/3012 ,  G06F9/30043 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3891

Abstract: Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.

公开(公告)号：US20170003971A1

公开(公告)日：2017-01-05

申请号：US15072670

申请日：2016-03-17

Applicant: International Business Machines Corporation

Inventor： Salma Ayub ,  Josh BOWMAN ,  Sundeep CHADHA ,  Dhivya JEGANATHAN ,  Cliff KUCHARSKI ,  Dung Q. NGUYEN

IPC: G06F9/38 ,  G06F1/10 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F1/10 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851

Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.

Abstract translation: 本文公开的技术描述了用于在处理器中交织指令标签的可变等待时间管线。 根据本文提出的一个实施例，指令标签与从发布队列发出指令的指令相关联。 确定延迟管中的多个位置之一。 管道存储一个或多个指令标签，每个指令标签与相应的指令相关联。 管道还基于每个相应指令的等待时间将指令标签存储在相应的位置。 指令标签存储在管道中确定的位置。

公开(公告)号：US20160378504A1

公开(公告)日：2016-12-29

申请号：US14833207

申请日：2015-08-24

Applicant: International Business Machines Corporation

Inventor： Jeffrey C. BROWNSCHEIDLE ,  Sundeep CHADHA ,  Maureen A. DELANEY ,  Dung Q. NGUYEN

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3855

Abstract: Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue queue stores instructions in a corresponding queue position. The first instruction includes a target instruction tag and at least a source instruction tag. The target instruction tag is stored in a table storing a plurality of target instruction tags associated with a corresponding instruction. Each stored target instruction tag specifies a logical register that stores a target operand. Upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with a second instruction, that the first instruction is dependent on the second instruction, a pointer to the first instruction is associated with the second instruction. The pointer is used to wake up the first instruction upon issue of the second instruction.

Abstract translation: 公开了用于在处理器中背对背发出指令的技术。 第一条指令存储在发布队列中的队列位置。 问题队列将指令存储在相应的队列位置。 第一指令包括目标指令标签和至少源指令标签。 目标指令标签存储在存储与相应指令相关联的多个目标指令标签的表中。 每个存储的目标指令标签指定存储目标操作数的逻辑寄存器。 在基于与第一指令相关联的源指令标记和与第二指令相关联的目标指令标记确定第一指令取决于第二指令时，指向第一指令的指针与第二指令相关联。 该指针用于在发出第二条指令时唤醒第一条指令。

公开(公告)号：US20160378503A1

公开(公告)日：2016-12-29

申请号：US14751730

申请日：2015-06-26

Applicant: International Business Machines Corporation

Inventor： Jeffrey C. BROWNSCHEIDLE ,  Sundeep CHADHA ,  Maureen A. DELANEY ,  Dung Q. NGUYEN

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3855

Abstract: Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue queue stores instructions in a corresponding queue position. The first instruction includes a target instruction tag and at least a source instruction tag. The target instruction tag is stored in a table storing a plurality of target instruction tags associated with a corresponding instruction. Each stored target instruction tag specifies a logical register that stores a target operand. Upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with a second instruction, that the first instruction is dependent on the second instruction, a pointer to the first instruction is associated with the second instruction. The pointer is used to wake up the first instruction upon issue of the second instruction.