公开(公告)号：US20040060024A1

公开(公告)日：2004-03-25

申请号：US10065202

申请日：2002-09-25

Applicant: International Business Machines Corporation

Inventor： Thomas R. Bednar ,  Scott W. Gould ,  David E. Lackey ,  Douglas W. Stout ,  Paul S. Zuchowski

IPC: G06F017/50

CPC classification number: G06F17/5045 ,  G06F17/5068

Abstract: A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.

Abstract translation: 公开了一种用于设计集成电路芯片的方法和结构。 该方法提供芯片设计，根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以创建电压岛，创建电压岛的平面图，评估平面图，重复划分和创建 取决于评估过程的结果，并输出电压岛规格表。

公开(公告)号：US20020101777A1

公开(公告)日：2002-08-01

申请号：US09731147

申请日：2000-12-05

Applicant: International Business Machines Corporation

Inventor： Darren L. Anand ,  John Edward Barth JR. ,  John Atkinson Fifield ,  Pamela Sue Gillis ,  Peter O. Jakobsen ,  Douglas Wayne Kemerer ,  David E. Lackey ,  Steven Frederick Oakland ,  Michael Richard Ouellette ,  William Robert Tonti

IPC: G11C007/20

CPC classification number: G11C29/80 ,  G11C29/802

Abstract: A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

Abstract translation: 使用来自远程保险丝盒的压缩数据初始化集成电路的方法和装置允许减少维修或定制集成电路所需的熔丝数量，并且允许将熔丝分组在由保险丝修复的宏之外。 保险丝的远程位置允许具有冗余修复能力的宏的放置灵活性，以及​​用于编程方便和电路布局促进的优选的熔丝组。 保险丝以行和列排列，并且表示控制字和游程长度压缩数据，以为每个保险丝提供更大量的修复点。 该数据可以串行加载到移位寄存器中，并转移到宏位置，以控制冗余电路的选择，以修复具有缺陷的集成电路或定制逻辑。

公开(公告)号：US20040135231A1

公开(公告)日：2004-07-15

申请号：US10248380

申请日：2003-01-15

Applicant: International Business Machines Corporation

Inventor： Brion L. Keller ,  Bernd K.F. Koenemann ,  David E. Lackey ,  Donald L. Wheater

IPC: H01L023/544

CPC classification number: G01R31/2884 ,  G01R31/2831 ,  G01R31/2889 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits. The stimulus busses can also be used to provide each chip with parallel serial scan data as well as power and other signals such as clock and enable and disable signals. Each chip control circuit provides the chip with power, bus clock, control, enable and response lines, can also connected to each chip via suitable lines in the kerfs.

Abstract translation: 将提供用于同时测试半导体晶片上的多个未切割芯片的多个通信路径的装置，其将同时允许每个这样的通信路径在使用最少数量的测试器接触的同时服务多于一个芯片。 本发明的这些和其它目的，特征和优点在其上具有多个切口隔离的集成芯片的半导体晶片中实现，每个所述芯片通过两个不同的刺激总线耦合到策略放置的管理电路中的至少两个不同的管理电路 ; 每个芯片通过布置在芯片之间的切口区域中的选择控制电路耦合到每个管理电路。 正是这种冗余可以显着降低相关管理或选择控制电路故障的可能性。 刺激总线还可以用于为每个芯片提供并行串行扫描数据以及功率和其他信号，如时钟和使能和禁止信号。 每个芯片控制电路为芯片提供电源，总线时钟，控制，使能和响应线路，还可以通过切口中的适当线路连接到每个芯片。

公开(公告)号：US20040060023A1

公开(公告)日：2004-03-25

申请号：US10065201

申请日：2002-09-25

Applicant: International Business Machines Corporation

Inventor： Thomas R. Bednar ,  Scott W. Gould ,  David E. Lackey ,  Douglas W. Stout ,  Paul S. Zuchowski

IPC: G06F017/50

CPC classification number: G06F17/5045

Abstract: A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.

公开(公告)号：US20030206051A1

公开(公告)日：2003-11-06

申请号：US10063504

申请日：2002-05-01

Applicant: International Business Machines Corporation

Inventor： Thomas Richard Bednar ,  Scott Whitney Gould ,  David E. Lackey ,  Douglas Willard Stout ,  Paul Steven Zuchowski

IPC: H01L025/00

CPC classification number: H03K19/0016

Abstract: A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.

Abstract translation: 一种用于缓冲处于待机或休眠模式的电压岛中的信号的方法和装置。 该设备使用由始终供电的全局电源电压供电的缓冲器，并且这样的缓冲器被放置在睡眠岛本身内。 睡眠岛可以处于与全局电压相同或不同的电压。

公开(公告)号：US20030015671A1

公开(公告)日：2003-01-23

申请号：US09908925

申请日：2001-07-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David E. Lackey ,  Theodore M. Levin ,  Leah M. Pastel

IPC: G21G005/00 ,  A61N005/00

CPC classification number: H01J37/3056 ,  H01J2237/304 ,  H01J2237/31737 ,  H01J2237/31742

Abstract: An apparatus for assisting backside focused ion beam (FIB) device modification is disclosed. The apparatus for assisting backside FIB device modification includes an FIB device modification circuit and a control circuit. The FIB device modification circuit includes an input, an output, an FIB input pad, and an FIB output pad. The FIB device modification circuit allows the input to be electrically connected to the output. The control circuit, which is coupled to the FIB device modification circuit, may include a jumper and a cut. The control circuit is preferably located in a proximity of a backside of a substrate to allow the jumper and the cut to be modified by an FIB machine.

公开(公告)号：US20020116690A1

公开(公告)日：2002-08-22

申请号：US09788925

申请日：2001-02-20

Applicant: International Business Machines Corporation

Inventor： David E. Lackey

IPC: G06F017/50

CPC classification number: G01R31/318536 ,  G01R31/318541

Abstract: A method of inserting test points in a circuit design includes selecting a node in the circuit design, determining a driver cell of the node, selecting a replacement cell for the driver cell and replacing the driver cell in the circuit design with the replacement cell. The replacement cell has the same function of the driver cell as well as a test point function. Additionally, the replacement cell is chosen so as not to break timing.

Abstract translation: 在电路设计中插入测试点的方法包括：选择电路设计中的节点，确定节点的驱动单元，选择驱动单元的替换单元，并用替换单元替换电路设计中的驱动单元。 替换单元具有与驱动单元相同的功能以及测试点功能。 此外，选择替换单元以便不打破时序。