公开(公告)号：US20160364332A1

公开(公告)日：2016-12-15

申请号：US14735429

申请日：2015-06-10

Applicant: International Business Machines Corporation

Inventor： Benjamin Carter Nowak ,  Guy Lynn Guthrie ,  Venkat R. Indukuru

IPC: G06F12/08

CPC classification number: G06F9/00 ,  G06F11/00 ,  G06F11/073 ,  G06F11/0793

Abstract: A hint bit detection and correction method uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.

Abstract translation: 提示位检测和校正方法使用两个附加位作为每个缓存目录的一部分。 这些位表示lwarx和stwcx指令（larx disp，stcx disp）。 当出现提示位事件时，根据这两个位的组合，可能会显示一个提示位错误。 一旦检测到提示位错误，就会发出软件中断，提示位校正方法识别和纠正不正确的提示位。

公开(公告)号：US20150127910A1

公开(公告)日：2015-05-07

申请号：US14170172

申请日：2014-01-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0811

Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.

Abstract translation: 一种用于操作数据处理系统的技术包括确定要从高速缓存受害的高速缓存行是否包括尚未记录的高可用性（HA）数据。 响应于确定要从缓存中受害的高速缓存线包括尚未记录的HA数据，HA数据的地址被写入HA脏地址数据结构，例如脏地址表（DAT）， 经由第一非阻塞通道在第一存储器中。 从缓存中受害的高速缓存线经由第二非阻塞通道被写入第二存储器。

公开(公告)号：US20150127906A1

公开(公告)日：2015-05-07

申请号：US14073553

申请日：2013-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016

Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.

Abstract translation: 用于操作高可用性（HA）数据处理系统的技术包括响应于在高速缓存处接收到HA注销指示，启动高速缓存的散步以定位包括HA数据的高速缓存中的高速缓存行。 响应于确定高速缓存行包括HA数据，高速缓存行的地址被记录在高速缓存中的缓冲器的第一部分中。 响应于缓冲器的第一部分达到确定的填充级别，缓冲器的第一部分的内容被记录到另一个存储器。 响应缓存中的所有缓存行被行走，高速缓存行走终止。

公开(公告)号：US10346255B2

公开(公告)日：2019-07-09

申请号：US16108583

申请日：2018-08-22

Applicant: International Business Machines Corporation

Inventor： Guy Lynn Guthrie ,  Naresh Nayar ,  Geraint North ,  Hugh Shen ,  William Starke ,  Phillip Williams

IPC: G06F12/00 ,  G06F11/14 ,  G06F12/0806 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/109 ,  G06F11/20 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/12

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

公开(公告)号：US10339009B2

公开(公告)日：2019-07-02

申请号：US16108236

申请日：2018-08-22

Applicant: International Business Machines Corporation

Inventor： Guy Lynn Guthrie ,  Naresh Nayar ,  Geraint North ,  Hugh Shen ,  William Starke ,  Phillip Williams

IPC: G06F12/00 ,  G06F11/14 ,  G06F12/0806 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/109 ,  G06F11/20 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/12

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

公开(公告)号：US10152385B2

公开(公告)日：2018-12-11

申请号：US14903833

申请日：2014-07-03

Applicant: International Business Machines Corporation

Inventor： Guy Lynn Guthrie ,  Naresh Nayar ,  Geraint North ,  Hugh Shen ,  William Starke ,  Phillip Williams

IPC: G06F12/00 ,  G06F11/14 ,  G06F12/0806 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/109 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/12 ,  G06F11/20

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

公开(公告)号：US09792208B2

公开(公告)日：2017-10-17

申请号：US14170172

申请日：2014-01-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/00 ,  G06F12/0804 ,  G06F11/14 ,  G06F12/0811 ,  G06F11/20

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0811

Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.

公开(公告)号：US09336142B2

公开(公告)日：2016-05-10

申请号：US14073531

申请日：2013-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/00 ,  G06F12/08 ,  G06F11/14

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0811

Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.

Abstract translation: 一种用于操作数据处理系统的技术包括确定要从高速缓存受害的高速缓存行是否包括尚未记录的高可用性（HA）数据。 响应于确定要从缓存中受害的高速缓存线包括尚未记录的HA数据，HA数据的地址被写入HA脏地址数据结构，例如脏地址表（DAT）， 经由第一非阻塞通道在第一存储器中。 从缓存中受害的高速缓存线经由第二非阻塞通道被写入第二存储器。

公开(公告)号：US20150127908A1

公开(公告)日：2015-05-07

申请号：US14073531

申请日：2013-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0811

Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.

Abstract translation: 一种用于操作数据处理系统的技术包括确定要从高速缓存受害的高速缓存行是否包括尚未记录的高可用性（HA）数据。 响应于确定要从缓存中受害的高速缓存线包括尚未记录的HA数据，HA数据的地址被写入HA脏地址数据结构，例如脏地址表（DAT）， 经由第一非阻塞通道在第一存储器中。 从缓存中受害的高速缓存线经由第二非阻塞通道被写入第二存储器。

公开(公告)号：US09921953B2

公开(公告)日：2018-03-20

申请号：US14848516

申请日：2015-09-09

Applicant: International Business Machines Corporation

Inventor： Benjamin Carter Nowak ,  Guy Lynn Guthrie ,  Venkat R Indukuru

IPC: G06F12/00 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0815

Abstract: A hint bit detection and correction method and system that uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.