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    Damascene gate multi-mesa MOSFET
    4.
    发明申请
    Damascene gate multi-mesa MOSFET 有权
    镶嵌门多台面MOSFET

    公开(公告)号：US20040061172A1

    公开(公告)日：2004-04-01

    申请号：US10262190

    申请日：2002-10-01

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Byeongju Park

    IPC分类号： H01L027/12

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78621 ,  H01L29/78636

    摘要： A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.

    摘要翻译： 公开了具有用于源极/漏极区域的掺杂侧壁的多台面FET结构及其形成方法。 在制造期间，源极和漏极侧壁的曝光使得能够均匀地掺杂整个侧壁，特别是当使用几何不依赖的掺杂方法（例如气相掺杂或等离子体掺杂）时。 所得到的器件具有深度独立和精确控制的阈值电压和电流密度，并且由于台面与现有技术中可能形成的台面相比可以非常高，所以每单位面积的硅可以具有非常高的电流。 提供了提供多台面FET结构的方法，其采用镶嵌栅极工艺或镶嵌栅极替代栅极工艺，而不是常规的减去蚀刻方法。

    Vertical dual gate field effect transistor
    5.
    发明申请
    Vertical dual gate field effect transistor 有权
    垂直双栅场效应晶体管

    公开(公告)号：US20030052364A1

    公开(公告)日：2003-03-20

    申请号：US09944665

    申请日：2001-08-31

    申请人： International Business Machines Corporation

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

    IPC分类号： H01L029/76

    CPC分类号： H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

    摘要： A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

    摘要翻译： 特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻或外延生长形成的半导体柱的相对侧上的潜在的独立栅极结构。 栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。 柱的上端由盖​​和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。 在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

    Dual gate logic device
    6.
    发明申请
    Dual gate logic device 失效
    双门逻辑器件

    公开(公告)号：US20020187610A1

    公开(公告)日：2002-12-12

    申请号：US09879590

    申请日：2001-06-12

    申请人： International Business Machines Corporation

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma

    IPC分类号： H01L021/336 ,  H01L021/8238

    CPC分类号： H01L29/66484 ,  H01L21/2807 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648

    摘要： The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.

    摘要翻译： 本发明的特征在于双栅极或双栅极逻辑器件，其包含一致的自对准并且具有恒定宽度的沟道的栅极导体。 本发明的方法还提供了选择性地蚀刻含锗栅极导体材料而不显着蚀刻相邻硅沟道材料的方法。 以这种方式，可以将栅极导体封装在电介质壳体中而不改变硅沟道的长度。 采用单晶硅晶片作为通道材料。 自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。 通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。 描述了其中可以选择性地蚀刻栅极导体材料而不蚀刻沟道材料的工艺。

    METHOD FOR IMAGE REVERSAL OF IMPLANT RESIST USING A SINGLE PHOTOLITHOGRAPHY EXPOSURE AND STRUCTURES FORMED THEREBY
    8.
    发明申请
    METHOD FOR IMAGE REVERSAL OF IMPLANT RESIST USING A SINGLE PHOTOLITHOGRAPHY EXPOSURE AND STRUCTURES FORMED THEREBY 审中-公开
    使用单一光刻曝光和其形成的结构的植入物的图像反转方法

    公开(公告)号：US20040256698A1

    公开(公告)日：2004-12-23

    申请号：US10709285

    申请日：2004-04-27

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Steven J. Holmes ,  Toshiharu Furukawa ,  Arpan P. Mahorowala ,  Dirk Pfeiffer

    IPC分类号： H01L021/336

    CPC分类号： H01L21/26513 ,  H01L21/823814

    摘要： A method for image reversal in semiconductor processing includes forming a first implant mask layer upon a semi-conductor substrate and forming a patterned photoresist layer over the first implant mask layer. Portions of the first implant mask layer not covered by the patterned photoresist layer are removed so as to expose non-patterned portions of the substrate. The photoresist layer is then removed, and a second implant mask layer is formed over the non-patterned portions of the substrate, wherein the first implant mask layer has an etch selectivity with respect to the second implant mask layer. The remaining portions of the first implant mask layer are removed to expose a reverse image of the substrate, including initially patterned portions of the substrate.

    摘要翻译： 半导体处理中的图像反转方法包括在半导体衬底上形成第一注入掩模层，并在第一注入掩模层上形成图案化的光致抗蚀剂层。 去除未被图案化光致抗蚀剂层覆盖的第一注入掩模层的部分，以暴露衬底的未图案化部分。 然后去除光致抗蚀剂层，并且在衬底的非图案化部分上形成第二注入掩模层，其中第一注入掩模层相对于第二注入掩模层具有蚀刻选择性。 去除第一注入掩模层的剩余部分以暴露衬底的反向图像，包括衬底的初始图案化部分。