公开(公告)号：US20250053803A1

公开(公告)日：2025-02-13

申请号：US18448390

申请日：2023-08-11

Applicant: International Business Machines Corporation

Inventor： Monodeep Kar ,  Subhankar Pal ,  Alper Buyuktosunoglu ,  Sanchari Sen

IPC: G06N3/08

Abstract: Processing zero weights within a data structure when performing a multiply and accumulate operation in a deep learning network as the result is itself a zero. Avoiding this step may save time and reduce power consumption in the training and operation of deep learning networks. An approach to zero-tile manipulation may be presented herein. An approach to permute and pack weighted data structures into zero-tile data structures may be presented. The zero-tiles may be configured in a structure which is optimized for the architecture of a parallel processing unit. The zero tile data structures may comprise vectors which instruct a the components in processing element to operate in a manner which prevents the element from expending energy when processing the zero tiles. An apparatus may also be presented in the immediate disclosure which can be configured to accept a zero-tile data structure.

公开(公告)号：US20230188146A1

公开(公告)日：2023-06-15

申请号：US17550493

申请日：2021-12-14

Applicant: International Business Machines Corporation

Inventor： Kyu-hyoun Kim ,  Mingu Kang ,  Ankur Agrawal ,  Monodeep Kar

IPC: H03M1/00

CPC classification number: H03M1/002

Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.

公开(公告)号：US20230058641A1

公开(公告)日：2023-02-23

申请号：US17406704

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： Monodeep Kar ,  Ankur Agrawal ,  Mingu Kang ,  Kyu-hyoun Kim

IPC: H03M1/38 ,  G06F17/16

Abstract: Techniques for performing analog-to-digital conversion are disclosed. For example, a method performs an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.

公开(公告)号：US20230083270A1

公开(公告)日：2023-03-16

申请号：US17474843

申请日：2021-09-14

Applicant: International Business Machines Corporation

Inventor： Ankur Agrawal ,  Mingu Kang ,  Kyu-hyoun Kim ,  Monodeep Kar

IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03M1/38

Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform, with a first accuracy, a first portion of a bitwise multiplication of first and second digital inputs and to perform, with a second accuracy different than the first accuracy, at least a second portion of the bitwise multiplication.

公开(公告)号：US20250077804A1

公开(公告)日：2025-03-06

申请号：US18458141

申请日：2023-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ankur Agrawal ,  Andrea Fasoli ,  Monodeep Kar ,  Kyu-hyoun Kim ,  Sergey Rylov ,  Chia-Yu Chen ,  Xiao Sun

IPC: G06G7/32

Abstract: A first circuit is configured to split a first integer value into a first coarse value and a first fine value, and split a second integer value into a second coarse value and a second fine value. A second circuit performs an analog multiply and accumulate (MAC) operation on the first and second coarse values to produce a first analog output, perform an analog MAC operation on the first coarse value and the second fine value to produce a second analog output, perform an analog MAC operation on the first fine value and the second coarse value to produce a third analog output, and perform an analog MAC operation on the first and second fine values together to produce a fourth analog output. A third circuit is configured to perform analog-to-digital (A/D) conversion on and combine the analog output signals to produce a reconstructed digital output signal.

公开(公告)号：US20240176584A1

公开(公告)日：2024-05-30

申请号：US18071230

申请日：2022-11-29

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Andrea Fasoli ,  Ankur Agrawal ,  Kyu-hyoun Kim ,  Chi-Chun LIU ,  Mauricio J. Serrano ,  Monodeep Kar ,  Naigang Wang ,  Leland Chang

IPC: G06F7/523

CPC classification number: G06F7/523

Abstract: An apparatus comprising: a first plurality of inputs representing an activation input vector; a second plurality of inputs representing a weight input vector; an analog multiplier-and-accumulator to generate a first analog voltage representing a first multiply-and-accumulate result for the said first inputs and the second inputs; a voltage multiplier that takes the said first analog voltage and produces a second analog voltage representing, a second multiply-and-accumulate result by multiplying at least one scaling factor to the first analog voltage; an analog to digital converter configured to convert the said second analog voltage multiply-and-accumulate result into a digital signal using a limited-precision operation during a neural network inference operation; and a hardware controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result, or a software controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result.

公开(公告)号：US11811416B2

公开(公告)日：2023-11-07

申请号：US17550493

申请日：2021-12-14

Applicant: International Business Machines Corporation

Inventor： Kyu-hyoun Kim ,  Mingu Kang ,  Ankur Agrawal ,  Monodeep Kar

IPC: H03M1/34 ,  H03M1/00

CPC classification number: H03M1/002

Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.