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    One-transistor synapse cell with weight adjustment
    3.
    发明授权
    One-transistor synapse cell with weight adjustment 有权

    公开(公告)号：US10395713B2

    公开(公告)日：2019-08-27

    申请号：US15859583

    申请日：2017-12-31

    Applicant: International Business Machines Corporation

    Inventor： Jin Ping Han ,  Xiao Sun ,  Teng Yang

    IPC: G06N3/06 ,  G11C11/22 ,  H03K19/177

    Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

    Neural network circuitry having floating point format with asymmetric range
    4.
    发明授权
    Neural network circuitry having floating point format with asymmetric range 有权

    公开(公告)号：US12217158B2

    公开(公告)日：2025-02-04

    申请号：US16558554

    申请日：2019-09-03

    Applicant: International Business Machines Corporation

    Inventor： Xiao Sun ,  Jungwook Choi ,  Naigang Wang ,  Chia-Yu Chen ,  Kailash Gopalakrishnan

    IPC: G06N3/063 ,  G06N3/084

    Abstract: An apparatus includes circuitry for a neural network that is configured to perform forward propagation neural network operations on floating point numbers having a first n-bit floating point format. The first n-bit floating point format has a configuration consisting of a sign bit, m exponent bits and p mantissa bits where m is greater than p. The circuitry is further configured to perform backward propagation neural network operations on floating point numbers having a second n-bit floating point format that is different than the first n-bit floating point format. The second n-bit floating point format has a configuration consisting of a sign bit, q exponent bits and r mantissa bits where q is greater than m and r is less than p.

    MULTI-KERNEL CONFIGURATION FOR CONVOLUTIONAL NEURAL NETWORKS
    6.
    发明申请
    MULTI-KERNEL CONFIGURATION FOR CONVOLUTIONAL NEURAL NETWORKS 审中-公开

    公开(公告)号：US20200265298A1

    公开(公告)日：2020-08-20

    申请号：US16279416

    申请日：2019-02-19

    Applicant: International Business Machines Corporation

    Inventor： Effendi Leobandung ,  Malte Rasch ,  Xiao Sun ,  Yulong Li ,  Zhibin Ren

    IPC: G06N3/063 ,  G06N3/04 ,  G06K9/62

    Abstract: Methods and systems of implementing a convolutional neural network are described. In an example, a structure may receive input signals and distribute the input signals to a plurality of unit cells. The structure may include a plurality of multi-kernel modules that may include a respective set of unit cells. A unit cell may correspond to an element of a kernel being implemented in the convolutional neural network and may include a storage component configured to store a weight of a corresponding element of the kernel. A first pass gate of the unit cell may be activated to pass a stored weight of the unit cell to a plurality of operation circuits in the corresponding unit cell, such that the stored weight may be applied to the input signals. The structure may generate a set of outputs based on the application of the stored weights to the input signals.

    One-transistor synapse cell with weight adjustment
    10.
    发明授权
    One-transistor synapse cell with weight adjustment 有权

    公开(公告)号：US10381061B2

    公开(公告)日：2019-08-13

    申请号：US15717023

    申请日：2017-09-27

    Applicant: International Business Machines Corporation

    Inventor： Jin Ping Han ,  Xiao Sun ,  Teng Yang

    IPC: G06N3/06 ,  G11C11/22 ,  H03K19/177

    Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

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