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    Stacked FET with Independent Gate Control
    2.
    发明申请
    Stacked FET with Independent Gate Control 有权

    公开(公告)号：US20230090346A1

    公开(公告)日：2023-03-23

    申请号：US17482928

    申请日：2021-09-23

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  JUNTAO LI ,  CHANRO PARK

    IPC分类号： H01L27/06 ,  H01L27/088 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/66

    摘要： Stacked FET devices having independent and shared gate contacts are provided. In one aspect of the invention, a stacked FET device includes: a bottom-level FET(s) having a bottom-level FET gate; a top-level FET(s) having a top-level FET gate, wherein an upper portion of the bottom-level FET gate is adjacent to the top-level FET gate; a dielectric sidewall spacer in between the upper portion of the bottom-level FET gate and the top-level FET gate; and a dielectric gate cap disposed over the bottom and top-level FET gates that includes a different dielectric material from the dielectric sidewall spacer. A device having at least one first stacked FET device and at least one second stacked FET device, and a method of forming a stacked FET device are also provided.

    NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK
    4.
    发明申请
    NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK 有权

    公开(公告)号：US20210359103A1

    公开(公告)日：2021-11-18

    申请号：US16876443

    申请日：2020-05-18

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  JUNTAO LI ,  Dechao Guo ,  Tao Li ,  Tsung-Sheng Kang

    IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

    摘要： Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical.

    PHASE CHANGE MEMORY CELL WITH SECOND CONDUCTIVE LAYER
    5.
    发明申请
    PHASE CHANGE MEMORY CELL WITH SECOND CONDUCTIVE LAYER 有权

    公开(公告)号：US20210020833A1

    公开(公告)日：2021-01-21

    申请号：US16515094

    申请日：2019-07-18

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： JUNTAO LI ,  Kangguo Cheng ,  Ruilong Xie ,  JUNLI WANG

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： A method may include forming a via opening in a dielectric layer, depositing a first conductive layer along a bottom and a sidewall of the via opening, depositing a second conductive layer on top of the first conductive layer. The method may further include recessing the first conductive layer to form a trench and exposing a sidewall of the second conductive layer, depositing a non-conductive material in the trench, and depositing a phase change material layer on top of the dielectric layer. The top surface of the second conductive layer may be in direct contact with a bottom surface of the phase change material layer.

    INNER SPACER FOR NANOSHEET TRANSISTORS
    6.
    发明申请
    INNER SPACER FOR NANOSHEET TRANSISTORS 审中-公开

    公开(公告)号：US20190214459A1

    公开(公告)日：2019-07-11

    申请号：US15868003

    申请日：2018-01-11

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： KANGGUO CHENG ,  CHOONGHYUN LEE ,  JUNTAO LI ,  PENG XU

    IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

    摘要： A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.