公开(公告)号：US20140110767A1

公开(公告)日：2014-04-24

申请号：US13659292

申请日：2012-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. ANDERSON ,  Andres BRYANT ,  Edward J. NOWAK ,  Scott R. STIFFLER

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L27/0924

Abstract: Bulk finFET well contacts with fin pattern uniformity and methods of manufacture. The method includes providing a substrate with a first region and a second region, the first region comprising a well with a first conductivity. The method further includes forming contiguous fins over the first region and the second region. The method further includes forming an epitaxial layer on at least one portion of the fins in the first region and at least one portion of the fins in the second region. The method further includes doping the epitaxial layer in the first region with a first type dopant to provide the first conductivity. The method further includes doping the epitaxial layer in the second region with a second type dopant to provide a second conductivity.

Abstract translation: 散装finFET良好的接触鳍片图案均匀性和制造方法。 该方法包括提供具有第一区域和第二区域的衬底，所述第一区域包括具有第一导电性的阱。 该方法还包括在第一区域和第二区域上形成连续的翅片。 该方法还包括在第一区域中的翅片的至少一部分上形成外延层，以及在第二区域中形成翅片的至少一部分。 该方法还包括在第一区域中用第一类型掺杂剂掺杂外延层以提供第一导电性。 该方法还包括在第二区域中用第二种掺杂剂掺杂外延层以提供第二导电性。

公开(公告)号：US20150221646A1

公开(公告)日：2015-08-06

申请号：US14686972

申请日：2015-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. ANDERSON ,  Andres BRYANT ,  Edward J. NOWAK ,  Jed H. RANKIN

IPC: H01L27/092 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0642

Abstract: A method includes forming at least one shallow trench isolation structure in a substrate to isolate adjacent different type devices. The method further includes forming a barrier trench structure in the substrate to isolate diffusions of adjacent same type devices. The method further includes spanning the barrier trench structure with material to connect the diffusions of the adjacent same type device, on a same level as the adjacent same type devices.

Abstract translation: 一种方法包括在衬底中形成至少一个浅沟槽隔离结构以隔离相邻的不同类型的器件。 该方法还包括在衬底中形成阻挡沟槽结构以隔离相邻相同类型器件的扩散。 该方法进一步包括将阻挡沟槽结构与材料连接，以将相邻相同类型器件的扩散连接在与相邻相同类型器件相同的水平上。

公开(公告)号：US20130175651A1

公开(公告)日：2013-07-11

申请号：US13780017

申请日：2013-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. ANDERSON ,  Andres BRYANT ,  William F. CLARK, JR. ,  John J. ELLIS-MONAGHAN ,  Edward J. NOWAK

IPC: H01L31/0232 ,  G06F17/50

CPC classification number: H01L31/0232 ,  G06F17/5045 ,  G06F17/5054 ,  H01L27/14632 ,  H01L27/14683 ,  H01L29/66545

Abstract: Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.

Abstract translation: 提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。 该方法包括在虚拟栅极结构上形成介电层。 该方法还包括在电介质层中形成一个或多个凹槽。 该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。 该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。

公开(公告)号：US20150214325A1

公开(公告)日：2015-07-30

申请号：US14167197

申请日：2014-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. ANDERSON ,  Andres BRYANT ,  Edward J. NOWAK

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Low capacitance finFET gate structures and methods of manufacturing. The method includes forming a layer of material on a substrate. The method further includes forming a dummy gate structure on the substrate which abuts the layer of material. The method further includes forming at least one spacer adjacent to the dummy gate structure and the layer of material. The method further includes removing the dummy gate structure and at least a portion of the layer of material to form an opening with a varying length. The method further includes forming a replacement gate structure with varying length by depositing gate material in the opening with the varying length.

Abstract translation: 低电容finFET门结构和制造方法。 该方法包括在基底上形成材料层。 该方法还包括在衬底上形成与栅极层相邻的虚拟栅极结构。 该方法还包括形成与虚拟栅极结构和材料层相邻的至少一个间隔物。 该方法还包括去除伪栅极结构和材料层的至少一部分以形成具有变化长度的开口。 该方法还包括通过在开口中以变化的长度沉积栅极材料来形成具有变化长度的替代栅极结构。

公开(公告)号：US20130119447A1

公开(公告)日：2013-05-16

申请号：US13736505

申请日：2013-01-08

Applicant: International Business Machines Corporation

Inventor： Brent A. ANDERSON ,  Andres BRYANT ,  William F. CLARK, JR. ,  John J. ELLIS-MONAGHAN ,  Edward J. NOWAK

IPC: H01L31/02

CPC classification number: H01L31/02 ,  H01L27/14614 ,  H01L27/14689

Abstract: A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.

Abstract translation: 提供了用于像素传感器单元的非均匀栅介质电荷，例如CMOS光学成像器，以及制造方法。 该方法包括在衬底上形成栅极电介质。 衬底包括源/漏区和光电池收集区。 该方法还包括在栅极电介质中形成不均匀的固定电荷分布。 该方法还包括在栅极电介质上形成栅极结构。

公开(公告)号：US20160111447A1

公开(公告)日：2016-04-21

申请号：US14514900

申请日：2014-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andres BRYANT ,  Brian J. GREENE ,  Jeffrey B. JOHNSON ,  Mickey H. YU

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/16 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02428 ,  H01L21/02532 ,  H01L21/845 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: Merged fin structures for finFET devices and methods of manufacture are disclosed. The method of forming the structure includes forming a plurality of fin structures on an insulator layer. The method further includes forming a faceted structure on adjacent fin structures of the plurality of fin structures. The method further includes spanning a gap between the faceted structures on the adjacent fin structures with a semiconductor material.

Abstract translation: 公开了FinFET器件的合并翅片结构和制造方法。 形成结构的方法包括在绝缘体层上形成多个翅片结构。 该方法还包括在多个翅片结构的相邻翅片结构上形成刻面结构。 该方法还包括利用半导体材料跨越相邻翅片结构上的小平面结构之间的间隙。

公开(公告)号：US20150035059A1

公开(公告)日：2015-02-05

申请号：US14520445

申请日：2014-10-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. ANDERSON ,  Andres BRYANT ,  Edward J. NOWAK

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/512 ,  H01L29/7841

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.

公开(公告)号：US20150028397A1

公开(公告)日：2015-01-29

申请号：US13949609

申请日：2013-07-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andres BRYANT ,  Lyndon R. LOGAN ,  Edward J. NOWAK ,  Robert R. ROBISON

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/7841

Abstract: Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.

Abstract translation: 提供零电容存储单元的方法。 制造半导体结构的方法包括通过掺杂第一种杂质的第一材料形成沟道区。 该方法包括通过用不同于第一种类型杂质的第二类型杂质掺杂第二材料来形成源极/漏极区域，其中第二材料具有比第一材料更小的带隙。 该方法包括在沟道区域和源极/漏极区域之间形成轻掺杂区域，其中轻掺杂区域包括第二材料。 该方法包括在通道区域上形成栅极，其中第二材料在栅极的边缘延伸。

公开(公告)号：US20130187243A1

公开(公告)日：2013-07-25

申请号：US13793185

申请日：2013-03-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. ANDERSON ,  Andres BRYANT ,  Edward J. NOWAK

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/512 ,  H01L29/7841

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.