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公开(公告)号：US11757431B2
公开(公告)日：2023-09-12
申请号：US17816146
申请日：2022-07-29
Applicant: International Business Machines Corporation
Inventor： Sudipto Chakraborty , John Francis Bulzacchelli , David James Frank
CPC classification number: H03K3/012 , G06N10/40 , H03D7/125 , H03D7/1441 , H03M1/66
Abstract: One or more systems, devices and/or methods of use provided herein relate to a device that can support a signal generation. A current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. Analog inputs and outputs of the DAC and upconverting mixer can be represented as currents, and the DAC can generate a baseband signal. The DAC and upconverting mixer each can comprise switching transistors of the same type, such as p-type metal-oxide semiconductor (PMOS) switching transistors. In one or more embodiments, a current source and a diode-connected transistor can be arranged in parallel in the current-mode signal path, and the current source passes a static current, while the diode-connected transistor passes both a static current and a dynamic current.
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公开(公告)号：US11736095B2
公开(公告)日：2023-08-22
申请号：US17987189
申请日：2022-11-15
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Daniel Ramirez , Sudipto Chakraborty
CPC classification number: H03K3/353 , H03K5/13 , H03K2005/00195
Abstract: A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.
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公开(公告)号：US20230208402A1
公开(公告)日：2023-06-29
申请号：US17816146
申请日：2022-07-29
Applicant: International Business Machines Corporation
Inventor： Sudipto Chakraborty , John Francis Bulzacchelli , David James Frank
Abstract: One or more systems, devices and/or methods of use provided herein relate to a device that can support a signal generation. A current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. Analog inputs and outputs of the DAC and upconverting mixer can be represented as currents, and the DAC can generate a baseband signal. The DAC and upconverting mixer each can comprise switching transistors of the same type, such as p-type metal-oxide semiconductor (PMOS) switching transistors. In one or more embodiments, a current source and a diode-connected transistor can be arranged in parallel in the current-mode signal path, and the current source passes a static current, while the diode-connected transistor passes both a static current and a dynamic current.
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公开(公告)号：US11574228B2
公开(公告)日：2023-02-07
申请号：US16865332
申请日：2020-05-02
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Sudipto Chakraborty , Rajiv Joshi
IPC: G06N10/00 , G06F15/80 , H03K19/195 , G06F1/20
Abstract: A quantum write controller includes an in-phase path that includes a first digital to analog converter (DAC) configured to receive an in-phase signal at a first frequency, a first mixer configured to create a third in phase frequency, a first combiner configured to combine an output of the first mixer with an output of a third mixer, and a second mixer configured to mix an output of the first combiner with a fourth in phase frequency. There is a quadrature path that includes a second DAC configured to receive a quadrature phase signal at the first frequency, a third mixer configured to create a third quadrature frequency, a second combiner configured to combine the output of the third mixer with the output of the first mixer, and a fourth mixer configured to mix an output of the second combiner with a fourth quadrature frequency.
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公开(公告)号：US20220294683A1
公开(公告)日：2022-09-15
申请号：US17199867
申请日：2021-03-12
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Sudipto Chakraborty , Rajiv Joshi
Abstract: Transmitters and methods of transmitting a polar-modulated signal include a driver to output a polar-modulated signal according to a phase-modulation signal and an amplitude-modulation signal. A voltage regulator is connected to the driver, with the amplitude-modulation signal controlling an input of the voltage regulator and with the amplitude-modulation signal further being combined with an output of the voltage regulator to control an amplitude of the output of the driver to compensate for bandwidth cutoff noise in the voltage regulator.
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Patent Agency Ranking
公开(公告)号：US11409940B2
公开(公告)日：2022-08-09
申请号：US17124484
申请日：2020-12-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Rajiv Joshi , Sudipto Chakraborty , Joseph Allen Glick , Pat Rosno
IPC: G06F30/398 , G06N10/00 , B82Y10/00
Abstract: A method of validating support circuits of a qubit array includes generating virtual control waveforms from one or more abstracted support circuits of the qubit array. An abstracted pulse sequence is created from the virtual control waveforms. The abstracted pulse sequence is converted into waveforms. The waveforms are sent to individual qubits of the qubit array. Output data from the qubit array is captured in response to the sent waveforms.
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公开(公告)号：US11379186B2
公开(公告)日：2022-07-05
申请号：US16735301
申请日：2020-01-06
Applicant: International Business Machines Corporation
Inventor： Sudipto Chakraborty , Rajiv Joshi
Abstract: Systems and methods to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a first current mode digital-to-analog converter (DAC) configured to multiply an input signal with a first current having a first amplitude to generate a first signal. The device can further include a second current mode DAC configured to multiply the input signal with a second current having a second amplitude to generate a second signal. The second amplitude can be less than the first amplitude. The device can further include a mixer configured to multiply the second signal with a clock signal to generate a third signal. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.
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公开(公告)号：US11315613B2
公开(公告)日：2022-04-26
申请号：US16806375
申请日：2020-03-02
Applicant: International Business Machines Corporation
Inventor： Sudipto Chakraborty , Rajiv Joshi , Steven J. Holmes , Bruce B. Doris
Abstract: Systems and methods for operating a digital-to-analog converter (DAC) are described. In an example, a device can receive a digital input. The device can generate a clock signal having frequency in radio frequency (RF) range. The device can combine the digital input with the clock signal to generate a first voltage signal. The device can convert the first voltage signal into a second voltage signal having at least two phases. The device can convert the second voltage signal into a current signal. The device can distribute the current signal to at least one current mode DAC.
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公开(公告)号：US20210194427A1
公开(公告)日：2021-06-24
申请号：US16726465
申请日：2019-12-24
Applicant: International Business Machines Corporation
Inventor： Sudipto Chakraborty , Rajiv Joshi , Steven J. Holmes , Bruce B. Doris
IPC: H03B5/12
Abstract: A remotely powered low power oscillator. According to an embodiment of the present invention, a method comprises an oscillator core, in a first environment, generating an oscillating signal; a power management system, in a second environment, supplying power to the oscillator core to operate the oscillator core; a sensing system, in the first environment, sensing one or more parameters of the oscillator core, and generating one or more signals representing said one or more parameters; transmitting the one or more signals from the sensing system to the second environment; and using the one or more signals in the second environment to control the power supplied to the oscillator core from the power management system.
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公开(公告)号：US11024354B1
公开(公告)日：2021-06-01
申请号：US16728041
申请日：2019-12-27
Applicant: International Business Machines Corporation
Inventor： Sudipto Chakraborty , Rajiv Joshi , Steven J. Holmes , Bruce B. Doris
Abstract: Circuits and methods are disclosed that, in embodiments, may be used for low power memory signal readout. In an embodiment, the circuit comprises a front end stage including an impedance conversion network for receiving a signal and providing voltage or current gain, and a wideband multiplier for receiving an output signal from the impedance conversion network and converting the output signal to differential output signals; and a baseband stage including a voltage mode mixer for receiving the differential output signals from the wideband multiplier and providing voltage gain, and a bandpass filter/amplifier for receiving a mixer output signal from the voltage mode mixer and filtering and amplifying the mixer output signal; and wherein DC voltages of the front-end stage are biased independently of a biasing of DC voltages of the baseband stage.
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