公开(公告)号：US09672910B2

公开(公告)日：2017-06-06

申请号：US14248377

申请日：2014-04-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Theodore Antonakopoulos ,  Nikolaos Papandreou ,  Charalampos Pozidis

IPC分类号： G06F12/00 ,  G11C14/00 ,  G11C7/10 ,  G11C11/56 ,  G11C13/00 ,  G11C5/06

CPC分类号： G11C14/009 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1003 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004

摘要： A memory system for storing data in a plurality N of memory chips. The memory system includes a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets.

公开(公告)号：US20140325124A1

公开(公告)日：2014-10-30

申请号：US14248377

申请日：2014-04-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Theodore Antonakopoulos ,  Nikolaos Papandreou ,  Charalampos Pozidis

IPC分类号： G06F3/06 ,  G11C14/00

CPC分类号： G11C14/009 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1003 ,  G11C7/1006 ,  G11C11/5678 ,  G11C13/0004

摘要： A memory system for storing data in a plurality N of memory chips. The memory system includes a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets.

摘要翻译： 一种用于将数据存储在多个存储器芯片中的存储器系统。 存储器系统包括K组的存储器芯片，其中K组的每组包括存储器芯片的数量M，其中N = K·M; 以及一个信号处理单元，具有数目为L的用于N个存储器芯片的信号处理数据的信号处理引擎，并且具有数据链接接口用于与每个K组进行对接。

公开(公告)号：US20150149816A1

公开(公告)日：2015-05-28

申请号：US14496273

申请日：2014-09-25

申请人： International Business Machines Corporation

发明人： Theodore Antonakopoulos ,  Thomas Mittelholzer ,  Nikolaos Papandreou ,  Charalampos Pozidis

IPC分类号： G06F11/07

CPC分类号： G06F11/073 ,  G06F3/06 ,  G06F11/008 ,  G06F11/076 ,  H04L1/0045

摘要： A multi-stage codeword detector for detecting codewords from read signals received from a multi-level memory device, includes a first detection stage configured for a coarse detection of a first codeword from a received read signal; a second detection stage configured for a fine detection of a second codeword from the received read signal; and a deciding entity configured to decide on using the second detection stage for the received read signal in dependence on a reliability indicator indicating a certain reliability level of the received read signal.

摘要翻译： 一种用于从从多级存储器件接收的读取信号中检测码字的多级码字检测器，包括：第一检测级，被配置用于从接收到的读取信号粗略地检测第一码字; 第二检测级，被配置为从所接收的读取信号中精细检测第二代码字; 以及决定实体，其被配置为根据指示所接收的读取信号的一定可靠性水平的可靠性指示符来决定对所接收的读取信号使用第二检测级。