公开(公告)号：US20160379867A1

公开(公告)日：2016-12-29

申请号：US15262034

申请日：2016-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： BRUCE DORIS ,  HONG HE ,  QING LIU

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/225 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

公开(公告)号：US20190378840A1

公开(公告)日：2019-12-12

申请号：US16548265

申请日：2019-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHIA-YU CHEN ,  BRUCE B. DORIS ,  HONG HE ,  RAJASEKHAR VENIGALLA

IPC: H01L27/092 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

公开(公告)号：US20150206877A1

公开(公告)日：2015-07-23

申请号：US14661590

申请日：2015-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： HONG HE ,  SHOGO MOCHIZUKI ,  CHIAHSUN TSENG ,  CHUN-CHEN YEH ,  YUNPENG YIN

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another.

Abstract translation: 具有非合并鳍扩展的半导体器件。 半导体器件包括形成在绝缘体层中的沟槽中的翅片，每个翅片具有均匀的晶体取向，并且在源极和漏极区域中的翅片帽垂直和横向地延伸超过沟槽。 各个翅片的翅片帽彼此分开。

公开(公告)号：US20170092713A1

公开(公告)日：2017-03-30

申请号：US14865667

申请日：2015-09-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHIA-YU CHEN ,  BRUCE B. DORIS ,  HONG HE ,  RAJASEKHAR VENIGALLA

IPC: H01L29/04 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

公开(公告)号：US20170092646A1

公开(公告)日：2017-03-30

申请号：US15285000

申请日：2016-10-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHIA-YU CHEN ,  BRUCE B. DORIS ,  HONG HE ,  RAJASEKHAR VENIGALLA

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417 ,  H01L29/04

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

公开(公告)号：US20170033104A1

公开(公告)日：2017-02-02

申请号：US15292768

申请日：2016-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： HONG HE ,  SHOGO MOCHIZUKI ,  CHIAHSUN TSENG ,  CHUN-CHEN YEH ,  YUNPENG YIN

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure.

Abstract translation: 半导体器件包括在绝缘体层中的沟槽中形成的多个散热片。 多个翅片中的每一个具有均匀的晶体取向和在垂直和横向延伸超过沟槽的源极和漏极区域中的鳍帽。 各个翅片的翅片帽彼此分开。 栅极结构形成在使源极和漏极区域露出的鳍片之上。 绝缘体层至少部分地覆盖栅极结构的侧壁。

公开(公告)号：US20150194504A1

公开(公告)日：2015-07-09

申请号：US14666464

申请日：2015-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： HONG HE ,  SHOGO MOCHIZUKI ,  CHIAHSUN TSENG ,  CHUN-CHEN YEH ,  YUNPENG YIN

IPC: H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.

Abstract translation: 用于形成具有非合并翅片延伸部分的半导体器件的方法。 用于形成半导体器件的方法包括在衬底的绝缘体层中形成沟槽。 鳍形成在沟槽中，并且虚拟栅极形成在鳍上，留下源极和漏极区域暴露。 翅片被蚀刻在周围绝缘体层的表面水平之下。 翅片延伸部从蚀刻的翅片外延生长。

公开(公告)号：US20200075598A1

公开(公告)日：2020-03-05

申请号：US16672994

申请日：2019-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHIA-YU CHEN ,  BRUCE B. DORIS ,  HONG HE ,  RAJASEKHAR VENIGALLA

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/18 ,  H01L29/165

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

公开(公告)号：US20150295065A1

公开(公告)日：2015-10-15

申请号：US14752095

申请日：2015-06-26

Applicant: International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： HONG HE ,  SHOGO MOCHIZUKI ,  CHIAHSUN TSENG ,  CHUN-CHEN YEH ,  YUNPENG YIN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

Abstract translation: 具有非合并翅片延伸的半导体器件及其形成方法。 用于形成半导体器件的方法包括在衬底上形成翅片; 在翅片上形成虚拟栅极，留下源极和漏极区域; 在低于周围绝缘体层的表面水平面处蚀刻散热片; 并从蚀刻的翅片外延生长翅片延伸部分。