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1.发明授权Data transmission apparatus for high-speed transmission of digital data and method for automatic skew calibration 有权用于数字数据高速传输的数据传输装置和自动偏斜校准方法公开(公告)号：US07278069B2
公开(公告)日：2007-10-02
申请号：US10425630
申请日：2003-04-30
申请人： Igor Anatolievich Abrosimov , Vasily Grigorievich Atyunin , Alexander Roger Deas , Ilya Vasilievich Klotchkov
发明人： Igor Anatolievich Abrosimov , Vasily Grigorievich Atyunin , Alexander Roger Deas , Ilya Vasilievich Klotchkov
CPC分类号： G01R31/31725 , G06F1/10 , H04L25/026
摘要： A data transmission apparatus and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data pattern and to compensate for production tolerances within the channel by altering the timing characteristics of the signal at either the transmitter or receiver as a function of the data. Time offsets between different signals that form the communication channel are measured for different frequencies and/or for different data patterns transmitted through the channel and stored to compensate for an inter-signal skew by performing relative alignment of the measured offsets to a main clock edge.
摘要翻译： 一种采用接收寄存器内的相位噪声特性的数据传输装置和方法，用于测量和控制作为数据模式的函数的信道的特性，并通过改变信号的时序特性来改变信道内的产生容限 发射器或接收器作为数据的函数。 针对不同的频率和/或通过信道发送的不同数据模式测量形成通信信道的不同信号之间的时间偏移，并通过执行所测量的偏移与主时钟边缘的相对对准来存储以补偿信号间偏斜。
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公开(公告)号：US06642764B2
公开(公告)日：2003-11-04
申请号：US10012779
申请日：2001-12-10
IPC分类号： H03K312
CPC分类号： H03K5/088
摘要： A high precision receiver with a means to reduce or compensate the skew caused by the receiver's hysteresis by using a dynamic reference that is varied depending on a current output signal. To avoid oscillation, the reference signal can be switched over with a certain delay.
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公开(公告)号：US06480021B2
公开(公告)日：2002-11-12
申请号：US09985726
申请日：2001-11-06
IPC分类号： H03K1716
CPC分类号： H04L25/028 , G01R31/31725 , G06F1/10 , H04B3/32 , H04L25/0292
摘要： The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips. A data transmission means for high-speed transmission of digital data is proposed, the data transmission means comprising: at least one driver for driving a transmission line; and a timing deskewing means connected thereto, wherein the timing deskewing means comprises a storage means for recording and storing information on skew caused by inter-symbol interference and cross-talk influence in the transmission line, for at least one data pattern transmitted through the transmission line; and an adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate for the above skew. The present invention allows to reduce the skew of signals at the end of a transmission line so as to compensate for the effects of cross-talk and various signal reflections, settling time influence, or other kind of inter-symbol interference like frequency dependent line resistance due to skin effect and provide thereby a high performance transmission means for high speed transmission of digital data.
摘要翻译： 本发明一般涉及数字数据的传输。 更具体地，本发明涉及集成电路（IC）或芯片之间的高速数据传输。提出了一种用于数字数据的高速传输的数据传输装置，数据传输装置包括：用于驱动数字数据的至少一个驱动器 传输线; 以及连接到其上的定时偏移装置，其中定时偏移装置包括用于记录和存储关于由传输线中的符号间干扰和串扰影响引起的偏斜的信息的存储装置，用于通过传输线传输的至少一个数据模式; 以及用于产生并对两个逻辑电平之间的信号转换的定时位置进行校正的校正装置，所述校正是基于存储在存储装置中的信息产生的，以补偿上述偏斜。本发明 允许减少传输线末端的信号偏斜，以补偿串扰和各种信号反射，稳定时间影响或其他类型的符号间干扰，如频率依赖的线路电阻由于皮肤的影响 从而提供用于数字数据的高速传输的高性能传输装置。
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公开(公告)号：US06741095B2
公开(公告)日：2004-05-25
申请号：US10151186
申请日：2002-05-21
IPC分类号： H03K1716
CPC分类号： H04L25/028 , H04L25/0278 , H04L25/0292
摘要： A transmission system and method for transmission of digital data with impedance matching at the terminal ends reduces reflected signals due to impedance mismatch at the terminating ends and due to impedance transition areas in the transmission line. The transmission system includes a transmission line having a driver end connected to a driving circuit and a receiving end connected to a receiving circuit, each said end having an adjustable termination means connected thereto On the driver end of the transmission line said adjustable termination means is incorporated in the driving circuit, while on the receiver end of the transmission line said adjustable termination means is connected in parallel with the receiving circuit. Thus, both the reflections produced on the ends of a transmission line and the reflections resulting from discontinuities within a transmission line will be terminated.
摘要翻译： 用于在终端端传输具有阻抗匹配的数字数据的传输系统和方法由于终端处的阻抗失配以及由于传输线路中的阻抗过渡区域而导致的反射信号减少。 传动系统包括传动线，其驱动端连接到驱动电路，接收端连接到接收电路，每个所述端部都具有连接到其上的可调终端装置。在传动线路的驱动器端，所述可调节端接装置被结合 在驱动电路中，在传输线的接收端，所述可调终端装置与接收电路并联连接。 因此，在传输线的端部产生的反射和由传输线内的不连续性引起的反射将被终止。
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公开(公告)号：US07271659B2
公开(公告)日：2007-09-18
申请号：US10997591
申请日：2004-11-24
IPC分类号： H03F1/14
CPC分类号： H03F3/45475 , H03F1/086 , H03F3/211 , H03F3/45188 , H03F2203/45648 , H03F2203/45696 , H03G5/04 , H03H15/00 , H03K2005/00208
摘要： An amplifier circuit for receiving an input signal and providing an output signal, comprises a main chain of logic stages with a plurality of nodes therebetween, and at least one auxiliary chain nested between one node in the main chain and another node, which is not the next node, to form a series of feed back or feed forward nested equalisation loops; whereby the input signal is fed serially down the main chain and is also fed through the said at least one auxiliary chain and summed to provide the output signal. The invention overcomes gain-bandwidth limits of the drive stages and bandwidth reductions that occur when analogue stages operating in a linear mode are concatenated.
摘要翻译： 一种用于接收输入信号并提供输出信号的放大器电路，包括主链逻辑级，其间具有多个节点，以及嵌套在主链中的一个节点和另一节点之间的至少一个辅助链，其不是 形成一系列反馈或前馈嵌套均衡环路; 由此输入信号被串行地向下馈送到主链，并且还通过所述至少一个辅助链进给并相加以提供输出信号。 本发明克服了以线性模式工作的模拟级连接时发生的驱动级和带宽减小的增益带宽限制。
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公开(公告)号：US07233599B2
公开(公告)日：2007-06-19
申请号：US10090829
申请日：2002-03-06
CPC分类号： G01R31/3191 , G01R31/31937 , H04B3/46
摘要： The present invention relates to high speed communications, in particular, to an interface device between a transmitting device and a receiving device of a transmission system, wherein the transmitting device is capable of automatic compensation of cross-talk timing errors in the interface device, for a group of signals, by using information stored in a storage attached to that interface device. Preferably, the data stored in said storage comprises data on interconnections between said first and second plurality of terminals and data on crosstalk timing errors in said transmission lines relating to a specific data pattern, for each of said stored interconnection.
摘要翻译： 本发明涉及高速通信，特别涉及传输系统的发送设备与接收设备之间的接口设备，其中发送设备能够自动补偿接口设备中的串扰定时错误，用于 一组信号，通过使用存储在附加到该接口设备的存储器中的信息。 优选地，存储在所述存储器中的数据包括关于所述第一和第二多个终端之间的互连的数据，以及关于每个所述存储的互连的与特定数据模式相关的所述传输线中的串扰定时误差的数据。
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公开(公告)号：US07092439B2
公开(公告)日：2006-08-15
申请号：US10079260
申请日：2002-02-21
CPC分类号： H04L25/4908
摘要： The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.
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8.发明授权Reference voltage generator for logic elements providing stable and predefined gate propagation time 有权用于提供稳定和预定义栅极传播时间的逻辑元件的参考电压发生器公开(公告)号：US07609119B2
公开(公告)日：2009-10-27
申请号：US10997592
申请日：2004-11-24
IPC分类号： H03L5/00
CPC分类号： H03K3/011 , H03K3/0322
摘要： A reference voltage generator and a method for generating a reference voltage for a logic device using the reference voltage generator is provided. The voltage reference generator includes a ring oscillator having a plurality of logic gates and a phase/frequency detector. A first reference voltage is generated on the basis of a phase/frequency difference between the phase/frequency of a reference clock and the phase/frequency of the ring oscillator. A second reference voltage is generated on the basis of a voltage swing of the oscillator circuit. Both reference voltages can be applied to the plurality of logic gates of the ring oscillator such that a constant delay is created through each logic gate of the logic device.
摘要翻译： 提供了一种参考电压发生器和用于使用参考电压发生器产生用于逻辑器件的参考电压的方法。 电压参考发生器包括具有多个逻辑门和相位/频率检测器的环形振荡器。 基于参考时钟的相位/频率与环形振荡器的相位/频率之间的相位/频率差产生第一参考电压。 基于振荡器电路的电压摆幅产生第二参考电压。 可以将两个参考电压施加到环形振荡器的多个逻辑门，使得通过逻辑器件的每个逻辑门产生恒定的延迟。
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公开(公告)号：US07203243B2
公开(公告)日：2007-04-10
申请号：US10384266
申请日：2003-03-10
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by the propagation delay of each gate and controlling driving transistors as a function of comparison of that history with input data so that, either the signal is driven into the transmission line at full strength, or at a level near the minimum needed to retain the state in the receiver.The advantage of the invention is that the line capacitance decays through the terminating resistors or discharge transistors, such that when the next state change is needed, then line has less stored energy needing to be discharged.
摘要翻译： 一种用于通过使用一串具有来自在每个门的传播延迟确定的点处获取的串中的抽头的门的存储器来存储所发送的数据的最近历史，并且控制驱动晶体管作为比较的函数来降低发送器的功耗的装置 具有输入数据的历史，使得信号以完全强度或接近保持接收器状态所需的最小值的速度被驱动到传输线中。
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公开(公告)号：US07702004B2
公开(公告)日：2010-04-20
申请号：US10730055
申请日：2003-12-09
IPC分类号： H04B1/38
CPC分类号： H04B3/23 , H04B1/58 , H04B3/03 , H04L25/085
摘要： Bidirectional differential point to point simultaneous high speed signalling is provided between integrated circuits with highly effective echo canceling. Each integrated circuit comprises a transmitter for transmitting a first signal to another integrated circuit and a receiver for receiving a second signal from the other integrated circuit. The transmitter has an output buffer; a receiver has a receiver buffer and is co-located on the same integrated circuit; and a differential buffer is coupled between the input of the transmitter buffer and the output of the receiver buffer. To increase the quality of receiving the second signal, a third signal adjusted in phase and amplitude is coupled at the output of the receive buffer, so that the echoing of the first signal is canceled. Preferably, the rise time of the third signal is also adjusted.
摘要翻译： 在具有高效回波消除的集成电路之间提供双向差分点对点同时高速信号。 每个集成电路包括用于将第一信号发送到另一集成电路的发射机和用于从另一集成电路接收第二信号的接收机。 发射机有一个输出缓冲器; 接收器具有接收器缓冲器并且位于同一集成电路上; 并且差分缓冲器耦合在发送器缓冲器的输入端和接收器缓冲器的输出端之间。 为了增加接收第二信号的质量，在接收缓冲器的输出处耦合相位和振幅调节的第三信号，从而消除第一信号的回波。 优选地，也调整第三信号的上升时间。
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