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公开(公告)号：US07702004B2
公开(公告)日：2010-04-20
申请号：US10730055
申请日：2003-12-09
IPC分类号： H04B1/38
CPC分类号： H04B3/23 , H04B1/58 , H04B3/03 , H04L25/085
摘要： Bidirectional differential point to point simultaneous high speed signalling is provided between integrated circuits with highly effective echo canceling. Each integrated circuit comprises a transmitter for transmitting a first signal to another integrated circuit and a receiver for receiving a second signal from the other integrated circuit. The transmitter has an output buffer; a receiver has a receiver buffer and is co-located on the same integrated circuit; and a differential buffer is coupled between the input of the transmitter buffer and the output of the receiver buffer. To increase the quality of receiving the second signal, a third signal adjusted in phase and amplitude is coupled at the output of the receive buffer, so that the echoing of the first signal is canceled. Preferably, the rise time of the third signal is also adjusted.
摘要翻译： 在具有高效回波消除的集成电路之间提供双向差分点对点同时高速信号。 每个集成电路包括用于将第一信号发送到另一集成电路的发射机和用于从另一集成电路接收第二信号的接收机。 发射机有一个输出缓冲器; 接收器具有接收器缓冲器并且位于同一集成电路上; 并且差分缓冲器耦合在发送器缓冲器的输入端和接收器缓冲器的输出端之间。 为了增加接收第二信号的质量，在接收缓冲器的输出处耦合相位和振幅调节的第三信号，从而消除第一信号的回波。 优选地，也调整第三信号的上升时间。
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2.发明授权Logic system with resistance to side-channel attack by exhibiting a closed clock-data eye diagram 失效逻辑系统通过展示闭合的时钟数据眼图来抵抗侧向通道攻击公开(公告)号：US08427194B2
公开(公告)日：2013-04-23
申请号：US13114399
申请日：2011-05-24
申请人： Alexander Roger Deas , David Coyne
发明人： Alexander Roger Deas , David Coyne
CPC分类号： H04L9/003 , G06F21/725 , G06F21/755
摘要： An improvement in the security of a logic system by minimizing observable features such as the power supply or electromagnetic radiation, so called, “side-channel attacks”. Specifically, the present invention comprises a technique and methods for reducing the ability of an intruder to monitor the relationship between currents in the system and the data in the system through the use of a randomized clock wherein the clock eye diagram is closed and without significant reduction in maximum operating speed compared to the reduction in maximum operating frequency that occurs when using conventional means of additive jitter. A system where the clock eye diagram is completely closed is provably more secure than systems where the clock eye diagram is partially open.
摘要翻译： 通过最小化诸如电源或电磁辐射等所谓的“侧信道攻击”的可观察特征来提高逻辑系统的安全性。 具体地，本发明包括一种技术和方法，用于降低入侵者通过使用随机时钟来监视系统中的电流与系统中的数据之间的关系的能力，其中时钟眼图被关闭并且没有显着的减少 与使用常规的相加抖动方式时发生的最大工作频率的降低相比，具有最大的操作速度。 时钟眼图完全关闭的系统比时钟眼图部分打开的系统更加安全。
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公开(公告)号：US4796004A
公开(公告)日：1989-01-03
申请号：US829624
申请日：1986-02-14
申请人： David Rich , Peter Staley , David Coyne
发明人： David Rich , Peter Staley , David Coyne
CPC分类号： G06F7/5095 , H03K3/356104 , H03K5/15066 , H03M3/43 , G06F2207/388 , H03M3/454 , H03M3/462
摘要： A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impulse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stages operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.
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公开(公告)号：US5831837A
公开(公告)日：1998-11-03
申请号：US860041
申请日：1997-06-09
CPC分类号： H04N3/185
摘要： A switch mode power supply comprises: a transformer (T1). A switch (Q4) alternately opens and closes a current path through a primary winding (L1) of the transformer in response to a pulse switching signal. An oscillator (110) generates the switching signal and synchronises the switching signal to a synchronisation signal (HSYNC') from an external source. A pulse width modulator (140) varies the pulse width of the switching signal in dependence upon a feedback signal indicative of a load on the power supply. A current limiter (150) turns off the switch to close the current path in response to current in the primary winding exceeding a threshold. Compensation means (160) is provided for varying the threshold in dependence upon the frequency of the synchronisation signal.
摘要翻译： PCT No.PCT / GB95 / 02205 Sec。 371日期：1997年6月9日 102（e）日期1997年6月9日PCT 1995年9月18日PCT公布。 出版物WO96 / 27232 日期1996年9月6日开关电源包括：变压器（T1）。 开关（Q4）响应于脉冲切换信号交替地打开和关闭通过变压器的初级绕组（L1）的电流路径。 振荡器（110）产生切换信号，并将切换信号与来自外部源的同步信号（HSYNC'）同步。 脉冲宽度调制器（140）根据指示电源上的负载的反馈信号改变开关信号的脉冲宽度。 电流限制器（150）关闭开关以响应于初级绕组中的电流超过阈值而闭合电流路径。 提供补偿装置（160），用于根据同步信号的频率改变阈值。
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公开(公告)号：US07987063B2
公开(公告)日：2011-07-26
申请号：US12107548
申请日：2008-04-22
申请人： David Coyne , Igor Abrosimov
发明人： David Coyne , Igor Abrosimov
CPC分类号： G01R31/2882 , G01R31/2834 , G01R31/31928 , H03K5/04 , H03K5/13 , H03K2005/00052
摘要： Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE includes a signal formatter with an SR latch having set an reset inputs each connected through or coupled to a number of signal channels. Each signal channel may receive a long pulse from a timing generator and generate a short pulse. Each signal channel has a current steering circuit that couples the short pulses to the set or reset ports of the latch. Because the outputs of each current steering circuit have a high impedance when not sending a pulse, multiplexing circuitry and/or circuitry to logically OR the outputs of separate signal channels are unnecessary. The hardware eliminated by this design simplifies and improves the ATE. Additionally, the latch can be set and reset in quick succession with good timing resolution.
摘要翻译： 用于在制造过程中测试半导体元件的自动测试设备（ATE）。 ATE在被测设备的测试点产生和测量信号。 ATE包括具有SR锁存器的信号格式化器，其设置复位输入，每个复位输入通过多个信号通道连接或耦合到多个信号通道。 每个信号通道可以从定时发生器接收长脉冲并产生短脉冲。 每个信号通道具有将短脉冲耦合到锁存器的置位或复位端口的电流转向电路。 因为当不发送脉冲时，每个电流转向电路的输出具有高阻抗，所以不需要多路复用电路和/或电路逻辑或分离信号通道的输出。 通过此设计消除的硬件简化和改进了ATE。 另外，锁存器可以快速连续地设置和复位，具有良好的时序分辨率。
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公开(公告)号：US20090261872A1
公开(公告)日：2009-10-22
申请号：US12107548
申请日：2008-04-22
申请人： David Coyne , Igor Abrosimov
发明人： David Coyne , Igor Abrosimov
IPC分类号： H03L7/00
CPC分类号： G01R31/2882 , G01R31/2834 , G01R31/31928 , H03K5/04 , H03K5/13 , H03K2005/00052
摘要： Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE includes a signal formatter with an SR latch having set and reset inputs each connected through or coupled to a number of signal channels. Each signal channel may receive a long pulse from a timing generator and generate a short pulse. Each signal channel has a current steering circuit that couples the short pulses to the set or reset ports of the latch. Because the outputs of each current steering circuit have a high impedance when not sending a pulse, multiplexing circuitry and/or circuitry to logically OR the outputs of separate signal channels are unnecessary. The hardware eliminated by this design simplifies and improves the ATE. Additionally, the latch can be set and reset in quick succession with good timing resolution.
摘要翻译： 用于在制造过程中测试半导体元件的自动测试设备（ATE）。 ATE在被测设备的测试点产生和测量信号。 ATE包括具有SR锁存器的信号格式化器，其具有每个通过多个信号通道连接或耦合到多个信号通道的置位和复位输入。 每个信号通道可以从定时发生器接收长脉冲并产生短脉冲。 每个信号通道具有将短脉冲耦合到锁存器的置位或复位端口的电流转向电路。 因为当不发送脉冲时，每个电流转向电路的输出具有高阻抗，所以不需要多路复用电路和/或电路逻辑或分离信号通道的输出。 通过此设计消除的硬件简化和改进了ATE。 另外，锁存器可以快速连续地设置和复位，具有良好的时序分辨率。
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公开(公告)号：US4748640A
公开(公告)日：1988-05-31
申请号：US831565
申请日：1986-02-21
申请人： Peter Staley , David Coyne
发明人： Peter Staley , David Coyne
CPC分类号： H04L25/03834 , G06F7/62 , H03K4/026 , H03K4/94 , H03K5/00006
摘要： The input digital signal is applied to a transition detector which causes an up/down counter to increment or decrement each time a transition is detected. The output of the counter is utilized to address a read only memory (ROM) which, in turn, generates binary words representing first and second integers. These binary words are used to control a programmable divider to generate an output having a frequency which moves between two values corresponding to the digital input. The rate at which the frequency changes between the two values is controlled by the ROM contents. In the implementation, the frequency changes with a raised cosine shape.
摘要翻译： 输入数字信号被施加到转换检测器，其使得每次检测到转变时使升/减计数器递增或递减。 计数器的输出被用于寻址只读存储器（ROM），其又产生表示第一和第二整数的二进制字。 这些二进制字用于控制可编程分频器以产生具有在对应于数字输入的两个值之间移动的频率的输出。 两个值之间频率变化的速率由ROM内容控制。 在实施中，频率随着升余弦形状而变化。
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公开(公告)号：US4467253A
公开(公告)日：1984-08-21
申请号：US337208
申请日：1982-01-05
申请人： David Coyne
发明人： David Coyne
CPC分类号： G11B5/59688
摘要： A decoder decodes and accurately scales so-called "tribit" servo signals after the receipt of only one tribit pattern without the use of A.G.C. by storing the peak values of the position indicating pulses the capacitors in first and second peak-and-hold circuits and thereafter discharging both capacitors with the same time constant, activating a sample-and-hold circuit to hold the value of the output of a difference amplifier at the instant when the output of a summing amplifier falls below a predetermined value.
摘要翻译： 在不使用A.G.C.的情况下，解码器解码并精确地缩放所谓的“三部分”伺服信号。 通过将电容器的位置指示脉冲的峰值存储在第一和第二峰值保持电路中，然后以相同的时间常数对两个电容器进行放电，激活采样和保持电路以保持输出的值 当加法放大器的输出下降到预定值以下时的差分放大器。
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