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    Nitride/oxide/nitride capacitor dielectric
    1.
    发明授权
    Nitride/oxide/nitride capacitor dielectric 失效
    氮化物/氧化物/氮化物电容器电介质

    公开(公告)号：US4882649A

    公开(公告)日：1989-11-21

    申请号：US174751

    申请日：1988-03-29

    申请人： Ih-Chin Chen ,  Bing W. Shen ,  Robert R. Doering

    发明人： Ih-Chin Chen ,  Bing W. Shen ,  Robert R. Doering

    IPC分类号： H01G4/20 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01G4/20 ,  H01L27/10829 ,  H01L29/945 ,  Y10T29/435

    摘要： An integrated circuit capacitor is disclosed which has improved leakage and storage characteristics. The dielectric material for the capacitor consists of a first layer of silicon nitride adjacent the lower plate, such as a silicon substrate, upon which a layer of silicon dioxide is formed. A second layer of silicon nitride is formed over the silicon dioxide layer, above which the second plate is formed. The layer of silicon dioxide may be formed by the partial oxidation of the first silicon nitride layer. The capacitor may be a planar capacitor, may be formed in a trench, or may be formed between two layers above the surface of the substrate.

    摘要翻译： 公开了一种具有改进的泄漏和存储特性的集成电路电容器。 用于电容器的电介质材料包括邻近下板的第一层氮化硅，例如硅衬底，在其上形成二氧化硅层。 在二氧化硅层上形成第二层氮化硅，在其上形成第二板。 二氧化硅层可以通过第一氮化硅层的部分氧化形成。 电容器可以是平面电容器，可以形成在沟槽中，或者可以形成在衬底表面之上的两层之间。

    High performance composed pillar dRAM cell
    3.
    发明授权
    High performance composed pillar dRAM cell 失效
    高性能组合的柱状DRAM单元

    公开(公告)号：US5103276A

    公开(公告)日：1992-04-07

    申请号：US200823

    申请日：1988-06-01

    申请人： Bing W. Shen ,  William F. Richardson ,  Robert R. Doering

    发明人： Bing W. Shen ,  William F. Richardson ,  Robert R. Doering

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row, separated therefrom by a gate dielectric film; the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.

    High performance composed pillar dRAM cell
    4.
    发明授权
    High performance composed pillar dRAM cell 失效
    高性能组合柱dRAM单元

    公开(公告)号：US5334548A

    公开(公告)日：1994-08-02

    申请号：US99822

    申请日：1993-07-30

    申请人： Bing W. Shen ,  William F. Richardson ,  Robert R. Doering

    发明人： Bing W. Shen ,  William F. Richardson ,  Robert R. Doering

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row, separated therefrom by a gate dielectric film; the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.

    摘要翻译： 公开了一种dRAM存储单元结构及其形成方法。 每个存储单元形成在柱上，其中存储板是由围绕每个柱的所有侧面的场板产生的反转区域，并由存储电介质膜分离。 场板形成为栅格形状，并且设置在围绕柱阵列的沟槽的底部，以用作阵列中的所有存储电容器的固定板。 每个支柱的顶部是位线连接到的扩散部分。 放置在场板上方的沟槽中并沿一个方向延伸的是字线。 每个字线由通过选择性CVD沉积钨的多晶硅细丝形成。 字线与其相关联的行中的柱紧邻地形成，通过栅极电介质膜与其分离; 字线通过比栅极电介质厚的电介质膜与相邻行分离，使得字线将引起反转区域与其相关行的顶部扩散之间的导通，但不会导致相邻行的导通。

    Method of making high performance composed pillar dRAM cell
    5.
    发明授权
    Method of making high performance composed pillar dRAM cell 失效
    制作高性能组合柱dRAM单元的方法

    公开(公告)号：US5106776A

    公开(公告)日：1992-04-21

    申请号：US700724

    申请日：1991-05-15

    申请人： Bing W. Shen ,  William F. Richardson ,  Robert R. Doering

    发明人： Bing W. Shen ,  William F. Richardson ,  Robert R. Doering

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row, separated therefrom by a gate dielectric film, the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.

    摘要翻译： 公开了一种dRAM存储单元结构及其形成方法。 每个存储单元形成在柱上，其中存储板是由围绕每个柱的所有侧面的场板产生的反转区域，并由存储电介质膜分离。 场板形成为栅格形状，并且设置在围绕柱阵列的沟槽的底部，以用作阵列中的所有存储电容器的固定板。 每个支柱的顶部是位线连接到的扩散部分。 放置在场板上方的沟槽中并沿一个方向延伸的是字线。 每个字线由通过选择性CVD沉积钨的多晶硅细丝形成。 字线与其相关联的行中的柱子紧邻地形成，通过栅极电介质膜与其隔开，字线通过比栅极电介质厚的电介质膜与相邻行分离，使得字线将导致 反转区域与其相关行的顶部扩散之间的导通，但不是相邻行。

    High performance composed pillar DRAM cell
    6.
    发明授权
    High performance composed pillar DRAM cell 失效
    高性能组合柱DRAM单元

    公开(公告)号：US5300450A

    公开(公告)日：1994-04-05

    申请号：US951639

    申请日：1992-09-25

    申请人： Bing W. Shen ,  William F. Richardson ,  Robert R. Doering

    发明人： Bing W. Shen ,  William F. Richardson ,  Robert R. Doering

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10864 ,  H01L27/10841

    摘要： A DRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row,, separated therefrom by a gate dielectric film; the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.

    摘要翻译： 公开了DRAM存储单元结构及其形成方法。 每个存储单元形成在柱上，其中存储板是由围绕每个柱的所有侧面的场板产生的反转区域，并由存储电介质膜分离。 场板形成为栅格形状，并且设置在围绕柱阵列的沟槽的底部，以用作阵列中的所有存储电容器的固定板。 每个支柱的顶部是位线连接到的扩散部分。 放置在场板上方的沟槽中并沿一个方向延伸的是字线。 每个字线由通过选择性CVD沉积钨的多晶硅细丝形成。 字线与其相关联的行中的柱紧邻地形成，通过栅极电介质膜与其分离; 字线通过比栅极电介质厚的电介质膜与相邻行分离，使得字线将引起反转区域与其相关行的顶部扩散之间的导通，但不会导致相邻行的导通。

    Trench memory cell
    7.
    发明授权
    Trench memory cell 失效
    沟槽记忆体

    公开(公告)号：US4958212A

    公开(公告)日：1990-09-18

    申请号：US292285

    申请日：1988-12-30

    申请人： Clarence W. Teng ,  William F. Richardson ,  Robert R. Doering ,  Ashwin H. Shah ,  Bing W. Shen ,  Mark Bordelon

    发明人： Clarence W. Teng ,  William F. Richardson ,  Robert R. Doering ,  Ashwin H. Shah ,  Bing W. Shen ,  Mark Bordelon

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10841

    摘要： An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).

    摘要翻译： 形成改进的存储单元布局（54），包括形成在半导体衬底（58）中的沟槽单元（60）。 存储单元布局（54）包括用于存储和访问电荷的位线（56）和字线（62）。 电荷存储在由导体（68），绝缘区（70）和半导体衬底（58）形成的电容器上。 位线（56）主要与沟槽单元（60）相切，或者可以围绕其周边。 字线（62）覆盖在沟槽单元（60）上并在其中延伸，并且还可以由窄于沟槽单元（60）的宽度形成。