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    Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation
    1.
    发明授权
    Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation 有权
    耦合到PE阵列的最上排中的相应PE的浮点累加器的行，用于执行附加操作

    公开(公告)号：US07769981B2

    公开(公告)日：2010-08-03

    申请号：US12045844

    申请日：2008-03-11

    申请人： Chun Gi Lyuh ,  Yil Suk Yang ,  Se Wan Heo ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Se Hoon Yoo

    发明人： Chun Gi Lyuh ,  Yil Suk Yang ,  Se Wan Heo ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Se Hoon Yoo

    IPC分类号： G06F15/80

    CPC分类号： G06F15/8007

    摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

    摘要翻译： 提供了一种用于支持浮点运算的并行处理器。 并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。 为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。 使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。 此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

    Highly energy-efficient processor employing dynamic voltage scaling
    2.
    发明申请
    Highly energy-efficient processor employing dynamic voltage scaling 有权
    采用动态电压调节的高能效处理器

    公开(公告)号：US20070150763A1

    公开(公告)日：2007-06-28

    申请号：US11520177

    申请日：2006-09-13

    申请人： Yil Suk Yang ,  Jong Dae Kim ,  Soon Il Yeo ,  Chun Gi Lyuh

    发明人： Yil Suk Yang ,  Jong Dae Kim ,  Soon Il Yeo ,  Chun Gi Lyuh

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

    摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.

    摘要翻译： 提供了一种高能效的处理器架构。 该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。 采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

    Highly energy-efficient processor employing dynamic voltage scaling
    3.
    发明授权
    Highly energy-efficient processor employing dynamic voltage scaling 有权
    采用动态电压调节的高能效处理器

    公开(公告)号：US07805620B2

    公开(公告)日：2010-09-28

    申请号：US11520177

    申请日：2006-09-13

    申请人： Yil Suk Yang ,  Jong Dae Kim ,  Soon Il Yeo ,  Chun Gi Lyuh

    发明人： Yil Suk Yang ,  Jong Dae Kim ,  Soon Il Yeo ,  Chun Gi Lyuh

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

    摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.

    摘要翻译： 提供了一种高能效的处理器架构。 该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。 采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

    Arithmetic method and device of reconfigurable processor
    4.
    发明授权
    Arithmetic method and device of reconfigurable processor 失效
    可重构处理器的算术方法和装置

    公开(公告)号：US07958179B2

    公开(公告)日：2011-06-07

    申请号：US11978878

    申请日：2007-10-30

    申请人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

    发明人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

    IPC分类号： G06F7/38

    CPC分类号： G06F7/57

    摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.

    摘要翻译： 提供了可重构处理器的算术方法和装置。 算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从ALU，乘法器和移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

    Arithmetic method and device of reconfigurable processor
    5.
    发明申请
    Arithmetic method and device of reconfigurable processor 失效
    可重构处理器的算术方法和装置

    公开(公告)号：US20080140745A1

    公开(公告)日：2008-06-12

    申请号：US11978878

    申请日：2007-10-30

    申请人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

    发明人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

    IPC分类号： G06F5/01

    CPC分类号： G06F7/57

    摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.

    摘要翻译： 提供了可重构处理器的算术方法和装置。 算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从所述ALU，所述乘法器和所述移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

    Multi-threshold CMOS latch circuit
    7.
    发明申请
    Multi-threshold CMOS latch circuit 失效
    多阈值CMOS锁存电路

    公开(公告)号：US20070126486A1

    公开(公告)日：2007-06-07

    申请号：US11607743

    申请日：2006-12-01

    申请人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    发明人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    IPC分类号： H03K3/00

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

    摘要翻译： 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

    Multi-threshold CMOS latch circuit
    8.
    发明授权
    Multi-threshold CMOS latch circuit 失效
    多阈值CMOS锁存电路

    公开(公告)号：US07391249B2

    公开(公告)日：2008-06-24

    申请号：US11607743

    申请日：2006-12-01

    申请人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    发明人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    IPC分类号： H03K3/289

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

    摘要翻译： 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

    Method and apparatus for managing reconfiguration data memory with a preservation data storing buffer in the target system and server
    9.
    发明授权
    Method and apparatus for managing reconfiguration data memory with a preservation data storing buffer in the target system and server 失效
    用于在目标系统和服务器中用保存数据存储缓冲器来管理重配置数据存储器的方法和装置

    公开(公告)号：US07793006B2

    公开(公告)日：2010-09-07

    申请号：US10917727

    申请日：2004-08-13

    申请人： Soon Il Yeo ,  Myung Shin Kwak ,  Jong Dae Kim

    发明人： Soon Il Yeo ,  Myung Shin Kwak ,  Jong Dae Kim

    IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F12/00 ,  G06F9/00 ,  G06F9/44

    CPC分类号： H04L67/025

    摘要： Provided are an apparatus and a method of managing a reconfiguration data memory. A space for a memory that stores configuration data used for reconfiguration of a target system is not provided in the target system. Instead the configuration data is stored in a separate server and, if required, the configuration data is transmitted to the target system through an Internet. Data that should be preserved after the reconfiguration among data contents stored in SoC internal and external memories of the target system is transferred to the server. The emptied space of the SoC internal and external memories is used as a configuration memory. After the reconfiguration, the preservation data is returned to its original position in the memories.

    摘要翻译： 提供了一种管理重配置数据存储器的装置和方法。 用于存储用于重新配置目标系统的配置数据的存储器的空间不在目标系统中提供。 而是将配置数据存储在单独的服务器中，如果需要，配置数据将通过Internet传输到目标系统。 在存储在目标系统的SoC内部和外部存储器中的数据内容重新配置后应保留的数据将传输到服务器。 SoC内部和外部存储器的空的空间用作配置存储器。 在重新配置之后，保存数据返回到其在存储器中的原始位置。