公开(公告)号：US07769981B2

公开(公告)日：2010-08-03

申请号：US12045844

申请日：2008-03-11

申请人： Chun Gi Lyuh ,  Yil Suk Yang ,  Se Wan Heo ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Se Hoon Yoo

发明人： Chun Gi Lyuh ,  Yil Suk Yang ,  Se Wan Heo ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Se Hoon Yoo

IPC分类号： G06F15/80

CPC分类号： G06F15/8007

摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

摘要翻译： 提供了一种用于支持浮点运算的并行处理器。 并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。 为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。 使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。 此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

公开(公告)号：US08731059B2

公开(公告)日：2014-05-20

申请号：US12105745

申请日：2008-04-18

申请人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Hoon Kim

发明人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Hoon Kim

IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N7/26 ,  H04N7/50 ,  H04N7/36

CPC分类号： H04N19/00521 ,  H04N19/102 ,  H04N19/122 ,  H04N19/134 ,  H04N19/436 ,  H04N19/57 ,  H04N19/61 ,  H04N19/86

摘要： An apparatus that calculates a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to multiple current frame macroblocks at a time is presented. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in multiple serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.

摘要翻译： 提出了一种计算能够相对于多个当前帧宏块同时计算SAD值的可变块的运动估计的绝对差（SAD）的装置。 该装置包括PE阵列单元，该PE阵列单元包括以矩阵的形式排列的至少一个处理元件（PE），并且并行地计算在多个串行当前帧宏块中提供的至少一个像素的SAD值，包括电流 帧宏块数据，参考帧宏块数据和参考帧搜索区域数据，并且将数据发送到在PE阵列单元中提供的每个PE，以及用于对提供在本地存储器中的数据进行命令的控制器 对应于至少一个像素，其中PE阵列单元中提供的每个PE执行计算。

公开(公告)号：US20070150763A1

公开(公告)日：2007-06-28

申请号：US11520177

申请日：2006-09-13

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Soon Il Yeo ,  Chun Gi Lyuh

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Soon Il Yeo ,  Chun Gi Lyuh

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.

摘要翻译： 提供了一种高能效的处理器架构。 该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。 采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

公开(公告)号：US07805620B2

公开(公告)日：2010-09-28

申请号：US11520177

申请日：2006-09-13

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Soon Il Yeo ,  Chun Gi Lyuh

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Soon Il Yeo ,  Chun Gi Lyuh

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.

摘要翻译： 提供了一种高能效的处理器架构。 该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。 采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

公开(公告)号：US20080133879A1

公开(公告)日：2008-06-05

申请号：US11906381

申请日：2007-10-01

申请人： Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim ,  Chun Gi Lyuh

发明人： Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim ,  Chun Gi Lyuh

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/30181 ,  G06F9/30189

摘要： Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register files. The SIMD parallel processor can selectively control data of register files required for any one of SIMD, single instruction single data (SISD), row, and column operations in response to an instruction. Since each of the SIMD, SISD, row, and column operations can be effectively performed according to the type of application, the SIMD parallel processor has excellent utility, efficiency, and flexibility.

摘要翻译： 提供了包括彼此连接的多个处理单元的单指令多数据（SIMD）并行处理器。 每个处理单元包括：指令寄存器; 指令解码器; 寄存器文件选择电路; 并注册文件。 SIMD并行处理器可以选择性地控制响应于指令的SIMD，单指令单数据（SISD），行和列操作中的任何一个所需的寄存器文件的数据。 由于可以根据应用类型有效地执行SIMD，SISD，行和列操作，所以SIMD并行处理器具有优异的效用，效率和灵活性。

公开(公告)号：US08150903B2

公开(公告)日：2012-04-03

申请号：US12136107

申请日：2008-06-10

申请人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： G06F7/57

CPC分类号： G06F7/57 ,  G06F7/5324 ,  G06F7/5338

摘要： Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.

摘要翻译： 提供了一种可重构运算单元和具有该可重配置运算单元的处理器。 可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。 可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积 产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。 算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

公开(公告)号：US07576582B2

公开(公告)日：2009-08-18

申请号：US11945387

申请日：2007-11-27

申请人： Dae Woo Lee ,  Yil Suk Yang ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Yil Suk Yang ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： H03K3/289

CPC分类号： H03K3/0375

摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

摘要翻译： 提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。 低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟 通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。 使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用 单阈值电压。

公开(公告)号：US20080291198A1

公开(公告)日：2008-11-27

申请号：US12100707

申请日：2008-04-10

申请人： Ik Jae Chun ,  Jung Hee Suk ,  Yil Suk Yang ,  Dae Woo Lee ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Woo Lee

发明人： Ik Jae Chun ,  Jung Hee Suk ,  Yil Suk Yang ,  Dae Woo Lee ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Woo Lee

IPC分类号： G06T15/00

CPC分类号： G06T15/005 ,  G06T2210/52

摘要： Provided is a method of performing three-dimensional (3D) graphics geometric transformation using a parallel processor having a plurality of Processing Elements (PEs). The method includes performing model/view transformation and projection transformation on a first group of vertex vectors using the parallel processor; calculating a value used for quaternion correction of the first group of vertex vectors using a general-use processor, and simultaneously performing model/view transformation and projection transformation on a second group of vertex vectors; performing quaternion correction and screen mapping on the first group of vertex vectors, and simultaneously calculating a value used for quaternion correction of the second group of vertex vectors using the general-use processor; and performing quaternion correction and screen mapping on the second group of vertex vectors.

摘要翻译： 提供了一种使用具有多个处理元件（PE）的并行处理器执行三维（3D）图形几何变换的方法。 该方法包括使用并行处理器对第一组顶点向量执行模型/视图变换和投影变换; 使用通用处理器计算用于第一组顶点矢量的四元数校正的值，并且同时对第二组顶点矢量执行模型/视图变换和投影变换; 对所述第一组顶点向量进行四元数校正和画面映射，并且使用所述通用处理器同时计算用于所述第二组顶点向量的四元数校正的值; 并对第二组顶点向量执行四元数校正和屏幕映射。

公开(公告)号：US20070126486A1

公开(公告)日：2007-06-07

申请号：US11607743

申请日：2006-12-01

申请人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

IPC分类号： H03K3/00

CPC分类号： H03K3/356156 ,  H03K3/012

摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

摘要翻译： 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

公开(公告)号：US07391249B2

公开(公告)日：2008-06-24

申请号：US11607743

申请日：2006-12-01

申请人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

IPC分类号： H03K3/289

CPC分类号： H03K3/356156 ,  H03K3/012

摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

摘要翻译： 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。