公开(公告)号：US06855581B2

公开(公告)日：2005-02-15

申请号：US10153975

申请日：2002-05-23

申请人： Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

发明人： Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

IPC分类号： H01L21/76 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.

摘要翻译： 本发明涉及使用其中绝缘膜和硅层依次层叠在硅衬底上的SOI结构的衬底的高压大功率集成电路器件的制造方法。 该方法包括以下步骤：在硅层上依次形成氧化物膜和光致抗蚀剂膜，然后使用沟槽掩模进行光刻工艺以对光刻胶膜进行图案化; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化膜，然后在图案化之后除去光致抗蚀剂膜; 使用所述图案化氧化膜作为掩模蚀刻所述硅层，直到所述绝缘膜暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜，执行退火处理并在整个表面上沉积多晶硅，使得沟槽被埋置; 并且顺序地去除多晶硅和氮化物膜，直到硅层暴露以使表面变平，从而形成用于在沟槽内的器件之间进行电隔离的器件隔离膜。 因此，本发明能够有效地降低高压大功率器件与逻辑CMOS器件之间的沟槽的隔离面积，能够容易地控制深井的浓度。

公开(公告)号：US06774697B2

公开(公告)日：2004-08-10

申请号：US10325929

申请日：2002-12-23

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

IPC分类号： H03L500

CPC分类号： H03K19/0016

摘要： The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.

摘要翻译： 本发明涉及输入和输出端口电路。 输入输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于 选择性地根据功率模式控制信号提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值确定信号的方向，以及输入/输出寄存器的值，输出控制 电路根据控制寄存器的值和信号方向控制电路的输出驱动，以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以使用单个输出驱动电路同时驱动，单输出驱动电路构成多级，由输出控制寄存器有选择地驱动。 因此，可以节省功耗。

公开(公告)号：US07403178B2

公开(公告)日：2008-07-22

申请号：US10817838

申请日：2004-04-06

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Sung Ku Kwon ,  Byoung Gon Yu

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Sung Ku Kwon ,  Byoung Gon Yu

IPC分类号： G09G3/30 ,  G09G3/20 ,  G09G3/22

CPC分类号： G09G3/30 ,  G09G2310/027 ,  G09G2320/0276

摘要： Provided is a source driver circuit for an active matrix electroluminescent (EL) display including a digital-to-analog converter/ramp circuit for converting a digital signal into an analog signal, and generating a ramp signal in this process, simultaneously, whereby high degree of integration would be possible since a conventional complicated circuit is not required and gray scale with the high characteristic can be implanted, regardless of a change of a temperature or a threshold voltage.

摘要翻译： 提供了一种用于有源矩阵电致发光（EL）显示器的源极驱动电路，其包括用于将数字信号转换为模拟信号的数模转换器/斜坡电路，并且在该过程中同时产生斜坡信号，由此高度 的集成是可能的，因为不需要常规的复杂电路，而不管温度或阈值电压的变化，都可以植入具有高特性的灰度级。

公开(公告)号：US06759714B2

公开(公告)日：2004-07-06

申请号：US10322232

申请日：2002-12-17

申请人： Sang Gi Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  II-Young Park ,  Byoung-Gon Yu ,  Jong Dae Kim

发明人： Sang Gi Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  II-Young Park ,  Byoung-Gon Yu ,  Jong Dae Kim

IPC分类号： H01L2972

CPC分类号： H01L21/76289 ,  H01L21/84 ,  H01L23/367 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, aiid removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.

摘要翻译： 提供半导体制造技术; 更具体地说，涉及具有使用绝缘体上硅（SOI）衬底的散热结构的半导体器件，以及制造半导体器件的方法。 本研究的装置和方法提供了具有高散热结构和高放热结构的半导体器件及其制造方法。 在研究中，通过在绝缘体上硅（SOI）衬底上形成集成电路，快速地通过隧道区域在衬底外部释放集成电路中产生的热和高频噪声，除去埋入 集成电路下的绝缘层形成隧道区。 当在隧道区域的上部和下部的表面上形成不均匀时，或者当具有优良导热性的空气或其它气体流入隧道区域时，可以进一步提高散热效率。

公开(公告)号：US07335945B2

公开(公告)日：2008-02-26

申请号：US11012695

申请日：2004-12-16

申请人： Dae Woo Lee ,  Tae Moon Roh ,  Sung Ku Kwon ,  Il Yong Park ,  Yil Suk Yang ,  Byoung Gon Yu ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Tae Moon Roh ,  Sung Ku Kwon ,  Il Yong Park ,  Yil Suk Yang ,  Byoung Gon Yu ,  Jong Dae Kim

IPC分类号： H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78645

摘要： Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.

摘要翻译： 提供一种多栅极MOS晶体管及其制造方法。 垂直堆叠在硅绝缘体（SOI）基板上的两个硅散热片，上硅片的四个侧表面和下硅片的三个侧表面用作通道。 因此，通道宽度增加，从而提高了器件的电流驱动能力，并且可以通过工艺的优化和稳定性来制造高性能纳米级半导体IC和高度集成的存储器IC。

公开(公告)号：US06887772B2

公开(公告)日：2005-05-03

申请号：US10721970

申请日：2003-11-24

申请人： Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  Il Yong Park ,  Byoung Gon Yu ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  Il Yong Park ,  Byoung Gon Yu ,  Jong Dae Kim

IPC分类号： H05B33/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/20 ,  H01L21/76 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  H01L27/088 ,  H01L27/1203

摘要： The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.

摘要翻译： 本发明涉及形成在SOI衬底上的高电压器件和低电压器件的结构及其制造方法，其特征在于SOI衬底中硅器件区域的低电压器件区域较高 比高压器件区域逐步，并且形成高压器件的硅器件​​区域的厚度等于低压器件中的源极和漏极的杂质的结深度。 因此，SOI衬底中的硅器件区域被分成高压区域和低电压区域，并且通过氧化生长方法在其间形成步骤，使得可以制造具有低结电容的高电压器件，并且低电压 与传统CMOS工艺兼容的器件和器件特性也可以同时进行。

公开(公告)号：US06617656B2

公开(公告)日：2003-09-09

申请号：US10179492

申请日：2002-06-24

申请人： Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Yil Suk Yang ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Yil Suk Yang ,  Jong Dae Kim

IPC分类号： H01L2978

CPC分类号： H01L29/0634 ,  H01L29/7835

摘要： The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

摘要翻译： 本发明提供一种具有晶格型漂移区域的EDMOS（延伸漏极MOS）器件及其制造方法。 在n沟道EDMOS（nEDMOS）的情况下，漂移区域具有晶格结构，其中具有高浓度的n晶格和具有低浓度的p晶格交替排列。 当施加漏极电压时，耗尽层被n晶格和p晶格的pn结突然延伸，使得整个漂移区域容易耗尽。 因此，器件的击穿电压增加，并且由于具有高浓度的n晶格，器件的导通电阻降低。

公开(公告)号：US06770529B2

公开(公告)日：2004-08-03

申请号：US10611502

申请日：2003-06-30

申请人： Dae Woo Lee ,  Tae Moon Roh ,  II Yong Park ,  Yil Suk Yang ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Tae Moon Roh ,  II Yong Park ,  Yil Suk Yang ,  Jong Dae Kim

IPC分类号： H01L218242

CPC分类号： H01L29/0634 ,  H01L29/7835

摘要： The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

摘要翻译： 本发明提供一种具有晶格型漂移区域的EDMOS（延伸漏极MOS）器件及其制造方法。 在n沟道EDMOS（nEDMOS）的情况下，漂移区域具有晶格结构，其中具有高浓度的n晶格和具有低浓度的p晶格交替排列。 当施加漏极电压时，耗尽层被n晶格和p晶格的pn结突然延伸，使得整个漂移区域容易耗尽。 因此，器件的击穿电压增加，并且由于具有高浓度的n晶格，器件的导通电阻降低。

公开(公告)号：US07461235B2

公开(公告)日：2008-12-02

申请号：US11144703

申请日：2005-06-06

申请人： Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Sang Heung Lee ,  Jong Dae Kim

发明人： Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Sang Heung Lee ,  Jong Dae Kim

IPC分类号： G06F15/76 ,  G06F1/32

CPC分类号： G06F9/3885 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/30141 ,  G06F9/30156 ,  G06F9/3822 ,  G06F9/3824 ,  Y02D10/171

摘要： Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units are enabled, power dissipation is reduced to enhance energy efficiency. Further, by use of a simple instruction format, hardware can be programmed as the parallel data path architecture for high energy efficiency, which satisfies both excellent performance and low power dissipation, thus elevating hardware flexibility.

摘要翻译： 提供了一种用于高能效的并行数据路径架构。 在该架构中，处理单元的多个并行处理单元和多个功能单元由指令控制并且并行处理以提高性能。 此外，由于只需要必要的处理单元和功能单元，所以功耗降低以提高能量效率。 此外，通过使用简单的指令格式，可以将硬件编程为用于高能量效率的并行数据路径体系结构，其既能满足优异性能又具有低功耗，从而提高硬件灵活性。

公开(公告)号：US07420403B2

公开(公告)日：2008-09-02

申请号：US11520165

申请日：2006-09-13

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Dae Woo Lee

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Dae Woo Lee

IPC分类号： H03K3/00

CPC分类号： H03K19/0013 ,  H03K3/356156 ,  H03K3/356182

摘要： A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit is presented that uses both low and high threshold inverters. The multi-threshold latch circuit includes: a low threshold forward clock inverter inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when a clock is in a first logic state; and a high threshold backward clock inverter forming a circular latch structure together with the forward clock inverter, and inverting an input-terminal logic state and applying the inverted logic state to an output logic state when the clock is in a second logic state.

摘要翻译： 提出了一种高可靠性，多阈值互补金属氧化物半导体（CMOS）锁存电路，其使用低和高阈值逆变器。 多阈值锁存电路包括：当门限处于第一逻辑状态时，低阈值正向时钟反相器反相输入端逻辑状态并将反相逻辑状态施加到输出端逻辑状态; 以及高阈值反向时钟反相器，与正向时钟反相器一起形成圆形锁存结构，并且在时钟处于第二逻辑状态时反相输入端逻辑状态并将反相逻辑状态应用于输出逻辑状态。