公开(公告)号：US20060242393A1

公开(公告)日：2006-10-26

申请号：US11110240

申请日：2005-04-20

申请人： Il Park ,  Pratap Pattnaik ,  Jong-Deok Choi

发明人： Il Park ,  Pratap Pattnaik ,  Jong-Deok Choi

IPC分类号： G06F9/00

CPC分类号： G06F9/3844 ,  G06F9/30061 ,  G06F9/324

摘要： An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-target branch and logic for reading the memory and identifying a repeated pattern in a plurality of target addresses for a multi-target branch. The information processing system further includes logic for predicting a next target address for the multi-target branch based on the repeated pattern that was identified.

摘要翻译： 公开了一种用于分支目标预测的信息处理系统。 信息处理系统包括用于存储条目的存储器，其中每个条目包括表示多目标分支的目标地址的历史的多个目标地址和用于读取存储器的逻辑，以及识别多个目标地址中的重复模式， 多目标分支。 信息处理系统还包括用于基于所识别的重复模式预测多目标分支的下一目标地址的逻辑。

公开(公告)号：US20110138101A1

公开(公告)日：2011-06-09

申请号：US12633428

申请日：2009-12-08

申请人： Kattamuri Ekanadham ,  Il Park ,  Pratap Pattnaik

发明人： Kattamuri Ekanadham ,  Il Park ,  Pratap Pattnaik

IPC分类号： G06F12/06

CPC分类号： G06F9/30007 ,  G06F12/0817 ,  G06F12/1027

摘要： A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.

摘要翻译： 公开了用于维持数据一致性的方法，系统和计算机程序产品，用于多节点处理系统，其中每个节点包括一个或多个组件。 在一个实施例中，该方法包括建立数据域，将一组组件分配给数据域，将相干消息从处理系统的第一组件发送到处理系统的第二组件，以及确定该第二组件 被分配给数据域。 在该实施例中，如果该第二组件被分配给数据域，则将相干消息传送到分配给数据域的所有组件，以维持这些组件之间的数据一致性。 在一个实施例中，如果将该第二组件分配给数据域，则将第一组件分配给数据域。

公开(公告)号：US08484422B2

公开(公告)日：2013-07-09

申请号：US12633428

申请日：2009-12-08

申请人： Kattamuri Ekanadham ,  Il Park ,  Pratap Pattnaik

发明人： Kattamuri Ekanadham ,  Il Park ,  Pratap Pattnaik

IPC分类号： G06F12/08

CPC分类号： G06F9/30007 ,  G06F12/0817 ,  G06F12/1027

摘要： A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.

摘要翻译： 公开了用于维持数据一致性的方法，系统和计算机程序产品，用于多节点处理系统，其中每个节点包括一个或多个组件。 在一个实施例中，该方法包括建立数据域，将一组组件分配给数据域，将相干消息从处理系统的第一组件发送到处理系统的第二组件，以及确定该第二组件 被分配给数据域。 在该实施例中，如果该第二组件被分配给数据域，则将相干消息传送到分配给数据域的所有组件，以维持这些组件之间的数据一致性。 在一个实施例中，如果将该第二组件分配给数据域，则将第一组件分配给数据域。

公开(公告)号：US07434037B2

公开(公告)日：2008-10-07

申请号：US11399979

申请日：2006-04-07

申请人： Il Park ,  Mauricio J. Serrano ,  Jong-Deok Choi

发明人： Il Park ,  Mauricio J. Serrano ,  Jong-Deok Choi

IPC分类号： G06F9/32

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3848

摘要： An information processing system includes a branch target buffer (BTB) comprising the last next address for the instruction and for receiving an indirect instruction address and providing a BTB predicted target; and next branch target table (NBTT) for storing potential branch targets based on a history of the branch and for providing an NBTT when the a BTB predicted target is not successful. In another embodiment a system comprising a plurality of branch prediction resources dynamically predicts the best resource appropriate for a branch. The method includes predicting a target branch for an indirect instruction address using a resource chosen among the plurality of branch prediction resources; and selectively inhibiting updates of the branch prediction resources whose prediction accuracy does not meet a threshold.

摘要翻译： 信息处理系统包括分支目标缓冲器（BTB），其包括用于该指令的最后一个下一个地址，并且用于接收间接指令地址并提供BTB预测目标; 以及用于基于分支的历史存储潜在的分支目标并且当BTB预测目标不成功时提供NBTT的下一分支目标表（NBTT）。 在另一个实施例中，包括多个分支预测资源的系统动态地预测适合于分支的最佳资源。 该方法包括使用在多个分支预测资源中选择的资源来预测间接指令地址的目标分支; 并且选择性地禁止预测精度不满足阈值的分支预测资源的更新。

公开(公告)号：US07900026B2

公开(公告)日：2011-03-01

申请号：US12246282

申请日：2008-10-06

申请人： Il Park ,  Mauricio J. Serrano ,  Jong-Deok Choi

发明人： Il Park ,  Mauricio J. Serrano ,  Jong-Deok Choi

IPC分类号： G06F9/32

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3848

摘要： A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction address to provide a first branch target prediction; a first branch table for capturing local past target information of an indirect branch in an encoded form; a second branch table which is a correlation table for storing potential branch targets based on a local branch history and which provides a second branch target prediction when the first branch target prediction is not successful; an exclusion predictor for inhibiting updates of inefficient entries; and a multiplexer to select the predicted target as output.

摘要翻译： 用于预测单个分支的多个目标的系统包括：分支目标缓冲器，其包括用于指令的先前的下一个地址并且接收间接指令地址以提供第一分支目标预测; 用于以编码形式捕获间接分支的当地过去目标信息的第一分支表; 第二分支表，其是基于本地分支历史存储潜在分支目标的相关表，并且当第一分支目标预测不成功时提供第二分支目标预测; 用于禁止更低效率条目的排除预测器; 以及选择预测目标作为输出的多路复用器。

公开(公告)号：US20080288760A1

公开(公告)日：2008-11-20

申请号：US12183995

申请日：2008-07-31

申请人： Il Park ,  Pratap C. Pattnaik ,  Jong-Deok Choi

发明人： Il Park ,  Pratap C. Pattnaik ,  Jong-Deok Choi

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/30061 ,  G06F9/324

摘要： An information processing system for branch target prediction includes: a first memory for storing entries for multi-target branch, wherein each entry includes a plurality of target addresses representing a history of target addresses for each single branch in the multi-target branch, and wherein said first memory stores an entry for the branch only if the branch is a multi-target branch; hardware logic for reading the memory and identifying a repeated pattern in each of the plurality of target addresses for the multi-target branch; logic for predicting a next target address for the multi-target branch based on the repeated pattern that was identified, using a pattern matching algorithm; and a second memory for storing information regarding whether a branch is a multi-target branch; wherein the logic for reading and the logic for predicting are executed only if the branch is the multi-target branch.

摘要翻译： 用于分支目标预测的信息处理系统包括：用于存储多目标分支的条目的第一存储器，其中每个条目包括表示多目标分支中的每个单个分支的目标地址的历史的多个目标地址，并且其中 所述第一存储器仅在所述分支是多目标分支时存储所述分支的条目; 用于读取存储器并识别用于多目标分支的多个目标地址中的每一个中的重复模式的硬件逻辑; 基于使用模式匹配算法识别的重复模式来预测多目标分支的下一目标地址的逻辑; 以及第二存储器，用于存储关于分支是否是多目标分支的信息; 其中仅当分支是多目标分支时才执行用于读取的逻辑和用于预测的逻辑。

公开(公告)号：US20090037708A1

公开(公告)日：2009-02-05

申请号：US12246282

申请日：2008-10-06

申请人： Il Park ,  Mauricio J. Serrano ,  Jong-Deok Choi

发明人： Il Park ,  Mauricio J. Serrano ,  Jong-Deok Choi

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3848

摘要： A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction address to provide a first branch target prediction; a first branch table for capturing local past target information of an indirect branch in an encoded form; a second branch table which is a correlation table for storing potential branch targets based on a local branch history and which provides a second branch target prediction when the first branch target prediction is not successful; an exclusion predictor for inhibiting updates of inefficient entries; and a multiplexer to select the predicted target as output.

摘要翻译： 用于预测单个分支的多个目标的系统包括：分支目标缓冲器，其包括用于指令的先前的下一个地址并且接收间接指令地址以提供第一分支目标预测; 用于以编码形式捕获间接分支的当地过去目标信息的第一分支表; 第二分支表，其是基于本地分支历史存储潜在分支目标的相关表，并且当第一分支目标预测不成功时提供第二分支目标预测; 用于禁止更低效率条目的排除预测器; 以及选择预测目标作为输出的多路复用器。

公开(公告)号：US07409535B2

公开(公告)日：2008-08-05

申请号：US11110240

申请日：2005-04-20

申请人： Il Park ,  Pratap C. Pattnaik ,  Jong-Deok Choi

发明人： Il Park ,  Pratap C. Pattnaik ,  Jong-Deok Choi

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/30061 ,  G06F9/324

摘要： An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-target branch and logic for reading the memory and identifying a repeated pattern in a plurality of target addresses for a multi-target branch. The information processing system further includes logic for predicting a next target address for the multi-target branch based on the repeated pattern that was identified.

摘要翻译： 公开了一种用于分支目标预测的信息处理系统。 信息处理系统包括用于存储条目的存储器，其中每个条目包括表示多目标分支的目标地址的历史的多个目标地址和用于读取存储器的逻辑，以及识别多个目标地址中的重复模式， 多目标分支。 信息处理系统还包括用于基于所识别的重复模式预测多目标分支的下一目标地址的逻辑。

公开(公告)号：US20090216956A1

公开(公告)日：2009-08-27

申请号：US12036476

申请日：2008-02-25

申请人： Kattamuri Ekanadham ,  Jennifer A. Navarro ,  Il Park ,  Chung-Lung Kevin Shum

发明人： Kattamuri Ekanadham ,  Jennifer A. Navarro ,  Il Park ,  Chung-Lung Kevin Shum

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6026

摘要： A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.

摘要翻译： 提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统，方法和计算机程序产品。 系统包括步幅图案检测器，用于检测作为连续高速缓存访​​问之间的差异的字节量的步幅大小的步幅图案。 系统还包括置信柜台。 该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。 该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器，将置信计数器与置信阈值进行比较，以及响应于达到置信阈值的置信度计数器请求高速缓存预取。 系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。

公开(公告)号：US20060049988A1

公开(公告)日：2006-03-09

申请号：US10983634

申请日：2004-11-09

申请人： Hyun Kim ,  Chul Kim ,  Jeong Seo ,  Il Park

发明人： Hyun Kim ,  Chul Kim ,  Jeong Seo ,  Il Park

IPC分类号： H01Q1/38

CPC分类号： H01Q1/243 ,  H01Q1/38 ,  H01Q9/0421 ,  H01Q21/0025

摘要： An antenna module, which minimizes a space, in an electronic apparatus set, occupied thereby without changing characteristics thereof, improves a degree of freedom of the installation structure thereof to increase the space utilization of the set, and achieves miniaturization and multi-functionality of electronic apparatuses, and an electronic apparatus having the antenna module. The antenna module includes a PCB (printed circuit board) made of nonconductive material having flexibility; an antenna element mounted at a designated position of the upper surface of the PCB; a ground line formed on the PCB so that the ground line is connected to a ground terminal of the antenna element, and provided with a joint portion formed at one end thereof; a feeder line formed on the PCB so that the feeder line is connected to a signal terminal of the antenna element, and provided with a joint portion formed at one end thereof; and a passive line, having a designated length, formed on the PCB in parallel with the feeder line. The joint portions of the ground line and the feeder line are bonded to designated positions of a set of the wireless electronic apparatus, and a portion of the antenna module having the antenna element mounted on the PCB is located outside the set.

摘要翻译： 在不改变其特性的情况下使电子设备组中的空间最小化的天线模块提高了其安装结构的自由度，从而提高了组件的空间利用率，并实现了电子设备的小型化和多功能化 装置和具有天线模块的电子装置。 天线模块包括由具有柔性的非导电材料制成的PCB（印刷电路板） 安装在PCB的上表面的指定位置的天线元件; 形成在PCB上的接地线，使得接地线连接到天线元件的接地端子，并且在其一端设置有接合部分; 形成在PCB上的馈电线，使得馈线与天线元件的信号端子连接，并且在其一端设置有接合部分; 以及具有指定长度的无源线，其与馈线相平行地形成在PCB上。 接地线和馈电线的接合部分接合到一组无线电子设备的指定位置，并且具有安装在PCB上的天线元件的天线模块的一部分位于组外部。