公开(公告)号：US20090286453A1

公开(公告)日：2009-11-19

申请号：US12385704

申请日：2009-04-16

申请人： Il-young Yoon ,  Tae-hoon Lee ,  Jae-ouk Choo

发明人： Il-young Yoon ,  Tae-hoon Lee ,  Jae-ouk Choo

IPC分类号： B24B49/04 ,  B24B1/00

CPC分类号： B24B37/042 ,  B24B49/04

摘要： In accordance with at least one example embodiment, a method of chemical-mechanical polishing includes re-polishing a polished layer on a wafer based on a measured thickness of the polished layer. In accordance with at least one example embodiment, an apparatus for chemical-mechanical polishing may include a thickness measuring unit configured to measure a thickness of a polished surface on a wafer and to determine a re-polishing time based on the measured thickness. In accordance with example embodiments, a thickness deviation between different lots, wafers, or chips inside a wafer is reduced regardless of the durability of a polishing pad, a polishing head, or a disk used in a polishing apparatus.

摘要翻译： 根据至少一个示例性实施例，化学机械抛光的方法包括基于所测量的抛光层的厚度在晶片上重新抛光抛光层。 根据至少一个示例性实施例，用于化学机械抛光的设备可以包括厚度测量单元，其被配置为测量晶片上的抛光表面的厚度并且基于测量的厚度来确定重新抛光时间。 根据示例性实施例，晶片内的不同批次，晶片或芯片之间的厚度偏差减小，而与研磨装置中使用的抛光垫，抛光头或盘的耐久性无关。

公开(公告)号：US20090305438A1

公开(公告)日：2009-12-10

申请号：US12457040

申请日：2009-05-29

申请人： Il-young Yoon ,  Tae-hoon Lee ,  Jae-ouk Choo

发明人： Il-young Yoon ,  Tae-hoon Lee ,  Jae-ouk Choo

IPC分类号： H01L21/306 ,  H01L21/762 ,  H01L21/66

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  H01L21/67219

摘要： A trench isolation method of a semiconductor device includes forming polishing prevention film patterns on a semiconductor substrate, etching the semiconductor device by using the polishing prevention film patterns as masks and forming trenches, and forming conformal insulation films on the semiconductor substrate and the polishing prevention film patterns by burying the trenches. The conformal insulation films are first polished using a first polishing pad by using a slurry including an abrasive having a polishing selection ratio with respect to the polishing prevention film patterns. The first polished conformal insulation films are second polished using a second polishing pad including an abrasive and by using the polishing prevention film patterns as polishing prevention films.

摘要翻译： 半导体器件的沟槽隔离方法包括在半导体衬底上形成防抛光膜图案，通过使用防抛光膜图案作为掩模蚀刻半导体器件并形成沟槽，并在半导体衬底和抛光防止膜上形成保形绝缘膜 埋葬壕沟的模式。 首先通过使用包括具有抛光选择比的研磨剂的浆料相对于抛光防止膜图案，使用第一抛光垫来抛光保形绝缘膜。 第一抛光保形绝缘膜使用包括研磨剂的第二抛光垫和通过使用抛光防止膜图案作为抛光防止膜进行第二抛光。

公开(公告)号：US20090305501A1

公开(公告)日：2009-12-10

申请号：US12471035

申请日：2009-05-22

申请人： Tae-hoon Lee ,  Il-Young Yoon ,  Jae-ouk Choo

发明人： Tae-hoon Lee ,  Il-Young Yoon ,  Jae-ouk Choo

IPC分类号： H01L21/768

CPC分类号： H01L21/7684 ,  H01L21/31053 ,  H01L21/3212

摘要： A method of fabricating a semiconductor device by using a chemical-mechanical polishing (CMP) process includes forming an insulating layer on a semiconductor wafer, etching the insulating layer to form via-holes, and forming a conductive layer on the insulating layer to fill the via-holes. The method further includes performing a first polishing process to etch the conductive layer until an upper surface of the insulating layer is exposed,, performing a second polishing process to etch the insulating layer to a predetermined thickness and performing a third polishing process to remove protrusions of the conductive layer.

摘要翻译： 通过使用化学机械抛光（CMP）工艺制造半导体器件的方法包括在半导体晶片上形成绝缘层，蚀刻绝缘层以形成通孔，并在绝缘层上形成导电层以填充 通孔。 该方法还包括执行第一抛光工艺以蚀刻导电层，直到绝缘层的上表面露出，执行第二抛光工艺以将绝缘层蚀刻到预定厚度，并执行第三抛光工艺以除去 导电层。

公开(公告)号：US20070128991A1

公开(公告)日：2007-06-07

申请号：US11634195

申请日：2006-12-06

申请人： Il-young Yoon ,  Hong-jae Shin ,  Se-young Lee ,  Jae-ouk Choo ,  Ja-eung Koo

发明人： Il-young Yoon ,  Hong-jae Shin ,  Se-young Lee ,  Jae-ouk Choo ,  Ja-eung Koo

IPC分类号： B24B1/00 ,  B24B29/00

CPC分类号： B24B37/245 ,  B24B37/26

摘要： A fixed abrasive polishing pad includes a base and a plurality of polishing layers on the base, wherein each polishing layer includes abrasive particles and apertures in a polishing surface of the polishing layer.

摘要翻译： 固定的研磨抛光垫包括基底和在基底上的多个抛光层，其中每个抛光层包括抛光层抛光表面中的研磨颗粒和孔。

公开(公告)号：US20080045018A1

公开(公告)日：2008-02-21

申请号：US11826899

申请日：2007-07-19

申请人： Il-young Yoon ,  Jae-ouk Choo ,  Ja-eung Koo

发明人： Il-young Yoon ,  Jae-ouk Choo ,  Ja-eung Koo

IPC分类号： H01L21/461

CPC分类号： H01L21/31053 ,  C09G1/02

摘要： A method of chemical-mechanical polishing (CMP) and a method of forming an isolation layer using the same are provided. The method of chemical-mechanical polishing includes performing a first chemical-mechanical polishing operation on an insulating layer having a zeta potential with a first polarity by supplying a first slurry on the insulating layer, wherein the first slurry includes a first abrasive and ionic surfactants having a zeta potential with a second polarity opposite to the first polarity. The method of forming an isolation layer includes forming a mask layer on a substrate, etching the substrate to a desired depth using the mask layer such that a trench is formed in the substrate, forming the insulating layer on the substrate and performing the first chemical-mechanical polishing operation described above.

摘要翻译： 提供化学机械抛光（CMP）的方法和使用其形成隔离层的方法。 化学机械抛光方法包括通过在绝缘层上提供第一浆料，对具有第一极性的ζ电位的绝缘层进行第一化学机械抛光操作，其中第一浆料包括第一磨料和离子表面活性剂，其具有 具有与第一极性相反的第二极性的ζ电位。 形成隔离层的方法包括在衬底上形成掩模层，使用掩模层将衬底蚀刻到所需的深度，使得在衬底中形成沟槽，在衬底上形成绝缘层，并执行第一化学 - 上述机械抛光操作。

公开(公告)号：US20070178644A1

公开(公告)日：2007-08-02

申请号：US11698070

申请日：2007-01-26

申请人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

发明人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

IPC分类号： H01L21/336

CPC分类号： H01L21/3212 ,  H01L21/76801 ,  H01L21/7684

摘要： A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

摘要翻译： 提供了当执行金属化学机械抛光（CMP）时具有降低（或最小）腐蚀性能的电介质或绝缘层的半导体器件及其制造方法。 半导体器件可以包括形成在衬底上的栅电极。 第一层间氧化物层可以形成在衬底上和栅电极之间。 可以在第一层间氧化物层上形成比第一层间氧化物层硬的第二层间氧化物层。 可以通过第二层间氧化物层和第一层间氧化物层形成插塞电极。

公开(公告)号：US07785951B2

公开(公告)日：2010-08-31

申请号：US11831223

申请日：2007-07-31

申请人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

摘要： Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

公开(公告)号：US20080153253A1

公开(公告)日：2008-06-26

申请号：US12003301

申请日：2007-12-21

申请人： Il-young Yoon ,  Jae-ouk Choo ,  Nam-jin Jung ,  Dong-hun Kim ,  Han-woo Lee ,  Gyu-nam Kim

发明人： Il-young Yoon ,  Jae-ouk Choo ,  Nam-jin Jung ,  Dong-hun Kim ,  Han-woo Lee ,  Gyu-nam Kim

IPC分类号： H01L21/762 ,  B24B1/00

CPC分类号： B24B37/26 ,  B24B37/044 ,  B24B37/245 ,  C09G1/00 ,  C09G1/04 ,  H01L21/31053 ,  H01L21/76224

摘要： A chemical mechanical polishing process and a method of fabricating a semiconductor device using the same are provided. The chemical mechanical polishing process includes applying a polishing activation solution with a reduced surface energy, wherein the polishing activation solution includes a surfactant; and polishing the object using the polishing activation solution. The method of fabrication includes forming a mask layer pattern on a semiconductor substrate, etching the substrate using the mask layer pattern as an etching mask, forming an insulating layer over a trench, and performing the chemical mechanical polishing above, wherein the object to be polished is the insulating layer.

摘要翻译： 提供化学机械抛光工艺和制造使用其的半导体器件的方法。 化学机械抛光工艺包括施加具有降低的表面能的抛光活化溶液，其中抛光活化溶液包括表面活性剂; 并使用抛光活化溶液抛光物体。 制造方法包括在半导体衬底上形成掩模层图案，使用掩模层图案蚀刻衬底作为蚀刻掩模，在沟槽上形成绝缘层，并进行上述化学机械抛光，其中待抛光的物体 是绝缘层。

公开(公告)号：US20080081476A1

公开(公告)日：2008-04-03

申请号：US11831223

申请日：2007-07-31

申请人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Il-young Yoon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L21/302 ,  H01L21/31

CPC分类号： H01L29/7843 ,  H01L21/31053 ,  H01L21/3185 ,  H01L21/823807

摘要： Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底上形成第一，第二和第三栅电极。 提供了覆盖第一栅电极和第三栅电极的至少第一部分的第一应力膜。 第一应力膜具有足够高的内部应力特性，以在与第一栅电极相对延伸的半导体衬底的第一部分中赋予净压应力。 还提供了第二应力膜。 第二应力膜覆盖第二栅电极和第三栅电极的至少第二部分。 第二应力膜具有足够高的内部应力特性，以在与第二栅电极相对延伸的半导体衬底的第二部分中施加净拉伸应力。 第二应力膜具有在与第三栅电极相邻的位置处与第一应力膜的上表面共面的上表面。

公开(公告)号：US07902609B2

公开(公告)日：2011-03-08

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L23/62

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。