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    System and method for forming a semiconductor with an analog capacitor using fewer structure steps
    1.
    发明申请
    System and method for forming a semiconductor with an analog capacitor using fewer structure steps 有权
    使用更少的结构步骤用模拟电容器形成半导体的系统和方法

    公开(公告)号：US20050221595A1

    公开(公告)日：2005-10-06

    申请号：US11145460

    申请日：2005-06-02

    申请人： Imran Khan ,  Louis Hutter ,  James Todd ,  Jozef Mitros ,  William Nehrer

    发明人： Imran Khan ,  Louis Hutter ,  James Todd ,  Jozef Mitros ,  William Nehrer

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/20

    CPC分类号： H01L29/66825 ,  H01L21/28273

    摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

    摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成氧化物层。 多晶硅层从氧化物层向外设置，其中多晶硅层形成浮栅。 PSG层从多晶硅层向外设置并平坦化。 该器件被图形蚀刻以形成电容器通道，其中电容器通道基本上设置在由多晶硅层形成的浮置栅极的上方。 在从多晶硅层向外设置的电容器通道中形成介电层。 形成可操作以充分充电电容器通道的钨插头。

    Vertical and lateral insulated-gate, field-effect transistors, systems and methods
    2.
    发明授权
    Vertical and lateral insulated-gate, field-effect transistors, systems and methods 失效
    垂直和横向绝缘栅，场效应晶体管，系统和方法

    公开(公告)号：US5272098A

    公开(公告)日：1993-12-21

    申请号：US952220

    申请日：1992-09-28

    申请人： Michael C. Smayling ,  James R. Todd ,  Louis Hutter

    发明人： Michael C. Smayling ,  James R. Todd ,  Louis Hutter

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/788 ,  H01L21/265

    CPC分类号： H01L29/66719 ,  H01L21/823456 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7883 ,  Y10S148/126

    摘要： A field effect transistor (147) is formed in a region of a second semiconductor layer (171), having a first conductivity type. A tank region (196) of a second conductivity type opposite the first conductivity type is formed in the semiconductor region (171), and defines a tank area on the face of the semiconductor layer (171). A first highly doped region (276) formed to be of the first conductivity type is formed within the region (171) and to be spaced from the tank region (196). A gate insulator layer (218) is formed on at least one selected portion of the face, this selected portion including a portion of the tank area (196). A conductive gate (246) is formed on the gate insulator layer over the selected portion of the face. At least one second highly doped region (278) is formed at the face within the tank area to be of the first conductivity type, and to have at least one lateral edge self-aligned to a corresponding one of the lateral edges of the gate (246 ). The tank area forms a channel between the first highly doped region (276) and the second highly doped region (278).

    摘要翻译： 场效应晶体管（147）形成在具有第一导电类型的第二半导体层（171）的区域中。 在半导体区域（171）中形成与第一导电类型相反的第二导电类型的槽区（196），并且限定半导体层（171）的表面上的槽区。 形成为第一导电类型的第一高掺杂区域（276）形成在区域（171）内并且与罐区域（196）间隔开。 栅极绝缘体层（218）形成在面的至少一个选定部分上，该选定部分包括罐区域（196）的一部分。 导电栅极（246）形成在栅极绝缘体层上面的所选择的部分上。 至少一个第二高度掺杂区域（278）形成在罐区域内的面上以具有第一导电类型，并且具有至少一个与栅极的相应一个边缘自对准的侧边缘（278） 246）。 罐区域在第一高度掺杂区域（276）和第二高度掺杂区域（278）之间形成通道。

    Structure for protecting integrated circuits from electro-static discharge
    3.
    发明授权
    Structure for protecting integrated circuits from electro-static discharge 失效
    用于保护集成电路免受静电放电的结构

    公开(公告)号：US5528064A

    公开(公告)日：1996-06-18

    申请号：US535367

    申请日：1995-09-28

    申请人： Frank L. Thiel ,  Michael R. Kay ,  Louis Hutter

    发明人： Frank L. Thiel ,  Michael R. Kay ,  Louis Hutter

    IPC分类号： H01L27/02 ,  H01L23/62 ,  H01L29/861

    CPC分类号： H01L27/0255 ,  H01L2924/0002

    摘要： An input protection circuit for a MOS device uses back-to-back zener diodes 30 and 40 with the anodes 130 and 150 connected and floating. This circuitry protects against positive and negative ESD events and does not interfere with the normal operation of the MOS device. The inventive circuit allows an improved gate operating range of the forward bias voltage of a first diode 30 plus the breakdown voltage of a second diode 40 below the supply voltage to the breakdown voltage of the first diode 30 plus the forward bias voltage of the second diode 40 above the supply voltage.

    摘要翻译： 用于MOS器件的输入保护电路使用背对背齐纳二极管30和40，阳极130和150连接并浮置。 该电路可防止正负ESD事件，并且不会干扰MOS器件的正常工作。 本发明的电路允许改进第一二极管30的正向偏置电压的栅极工作范围加上低于第一二极管30的击穿电压的第二二极管40的击穿电压加上第二二极管的正向偏置电压 40以上电源电压。