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1.发明申请System and method for forming a semiconductor with an analog capacitor using fewer structure steps 有权使用更少的结构步骤用模拟电容器形成半导体的系统和方法公开(公告)号：US20050221595A1
公开(公告)日：2005-10-06
申请号：US11145460
申请日：2005-06-02
申请人： Imran Khan , Louis Hutter , James Todd , Jozef Mitros , William Nehrer
发明人： Imran Khan , Louis Hutter , James Todd , Jozef Mitros , William Nehrer
IPC分类号： H01L21/28 , H01L21/336 , H01L21/20
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.
摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成氧化物层。 多晶硅层从氧化物层向外设置，其中多晶硅层形成浮栅。 PSG层从多晶硅层向外设置并平坦化。 该器件被图形蚀刻以形成电容器通道，其中电容器通道基本上设置在由多晶硅层形成的浮置栅极的上方。 在从多晶硅层向外设置的电容器通道中形成介电层。 形成可操作以充分充电电容器通道的钨插头。
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公开(公告)号：US08131623B2
公开(公告)日：2012-03-06
申请号：US13065848
申请日：2011-03-30
申请人： Amy Caruso , James Todd , Matthew Naughton , Judith Zaiken , Richard Byrne
发明人： Amy Caruso , James Todd , Matthew Naughton , Judith Zaiken , Richard Byrne
IPC分类号： G06Q40/00
摘要： The present invention relates to systems and methods for administering combination annuity products and to combination annuity products themselves. Certain embodiments of the invention can be used in connection with variable universal life insurance and variable life insurance contracts.
摘要翻译： 本发明涉及用于组合年金产品和组合年金产品本身的系统和方法。 本发明的某些实施例可用于可变通用人寿保险和可变人寿保险合同。
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公开(公告)号：US07383643B2
公开(公告)日：2008-06-10
申请号：US11088226
申请日：2005-03-23
IPC分类号： F26B5/04
CPC分类号： F26B5/048 , F26B5/045 , F26B9/066 , F26B2210/14
摘要： An apparatus and method is provided to dry veneer or other items by vaporization of moisture in the item. Apparatus has an insulated chamber with a frame and a drawer with a door. A mesh surface of the drawer supports item for drying with a heater at sub-atmospheric pressure inside of the chamber. Item is placed on the layer of mesh of the drawer of the apparatus and secured with fasteners such as another layer of mesh. The drawer with fastened item is placed into the chamber of the apparatus. With the drawer fully engaged within the chamber, the drying apparatus is closed with an airtight seal. A pump draws a vacuum in the chamber and heat is directed at the item to raise the temperature of the item to less than 160° F., particularly between 120° F. to 150° F. Apparatus can dry veneer in less than five minutes.
摘要翻译： 提供了一种装置和方法，用于通过物品中的水分蒸发来干燥胶合板或其它物品。 设备具有带框架的绝缘室和带门的抽屉。 抽屉的网眼表面支撑用于在室内的低于大气压的加热器干燥的物品。 将物品放置在设备的抽屉的网格层上，并用诸如另一层网的紧固件固定。 带有紧固件的抽屉放置在设备的室内。 当抽屉完全接合在室内时，干燥装置用气密密封封闭。 泵在室内抽真空，热量指向物品，以将物品的温度升高至小于160°F，特别是120°F至150°F。设备可在不到五分钟内干燥单板 。
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4.发明申请公开(公告)号：US20050064670A1
公开(公告)日：2005-03-24
申请号：US10669111
申请日：2003-09-23
申请人： Shanjen Pan , James Todd , Sameer Pendharkar , Tsutomu Kubota , Pinghai Hao
发明人： Shanjen Pan , James Todd , Sameer Pendharkar , Tsutomu Kubota , Pinghai Hao
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/0653 , H01L29/0847 , H01L29/0852 , H01L29/1033 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/7835
摘要： Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.
摘要翻译： 提供消耗漏极扩展MOS晶体管器件及其制造方法，其中补偿沟道区域设置有p型和n型掺杂剂以便于在Vgs = 0时耗尽操作，并且将调整区域注入到衬底中 厚栅电介质结构的通道侧端用于提高击穿电压额定值。 补偿通道区域由n阱和p阱的重叠植入物形成，并且使用具有暴露调整区域的掩模的Vt调整植入物形成调整区域。
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公开(公告)号：US20060041961A1
公开(公告)日：2006-02-23
申请号：US11087099
申请日：2005-03-22
申请人： Mark Abad , Jason Cotter , Robert D'Ordine , Angie Ferguson , Barry Goldman , Karen Hartsuyker , Balasulojini Karunanandaa , Susan Norris , Steven Rounsley , Joshua Stein , James Todd , Li Zhou
发明人： Mark Abad , Jason Cotter , Robert D'Ordine , Angie Ferguson , Barry Goldman , Karen Hartsuyker , Balasulojini Karunanandaa , Susan Norris , Steven Rounsley , Joshua Stein , James Todd , Li Zhou
CPC分类号： C12N15/8261 , C07K14/415 , C12N15/8271 , C12N15/8273 , Y02A40/146
摘要： Transgenic seed for crops with improved traits are provided by trait-improving recombinant DNA where plants grown from such transgenic seed exhibit one or more improved traits as compared to a control plant. Of particular interest are transgenic plants that have increased yield. The present invention also provides recombinant DNA molecules for expression of a protein, and recombinant DNA molecules for expression of mRNA complementary to at least a portion of an mRNA native to the target plant for use in gene suppression to suppress the expression of a protein.
摘要翻译： 具有改良性状的作物的转基因种子由改良重组DNA提供，其中与对照植物相比，从这种转基因种子生长的植物表现出一种或多种改良的性状。 特别感兴趣的是具有增加的产量的转基因植物。 本发明还提供了用于表达蛋白质的重组DNA分子和用于表达与目标植物天然的mRNA的至少一部分互补的mRNA的重组DNA分子，以用于基因抑制以抑制蛋白质的表达。
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公开(公告)号：US20050217136A1
公开(公告)日：2005-10-06
申请号：US11088226
申请日：2005-03-23
CPC分类号： F26B5/048 , F26B5/045 , F26B9/066 , F26B2210/14
摘要： An apparatus and method is provided to dry veneer or other items by vaporization of moisture in the item. Apparatus has an insulated chamber with a frame and a drawer with a door. A mesh surface of the drawer supports item for drying with a heater at sub-atmospheric pressure inside of the chamber. Item is placed on the layer of mesh of the drawer of the apparatus and secured with fasteners such as another layer of mesh. The drawer with fastened item is placed into the chamber of the apparatus. With the drawer fully engaged within the chamber, the drying apparatus is closed with an airtight seal. A pump draws a vacuum in the chamber and heat is directed at the item to raise the temperature of the item to less than 160° F., particularly between 120° F. to 150° F. Apparatus can dry veneer in less than five minutes.
摘要翻译： 提供了一种装置和方法，用于通过物品中的水分蒸发来干燥胶合板或其它物品。 设备具有带框架的绝缘室和带门的抽屉。 抽屉的网眼表面支撑用于在室内的低于大气压的加热器干燥的物品。 将物品放置在设备的抽屉的网格层上，并用诸如另一层网的紧固件固定。 带有紧固件的抽屉放置在设备的室内。 当抽屉完全接合在室内时，干燥装置用气密密封封闭。 泵在室内抽真空，热量指向物品，以将物品的温度升高至小于160°F，特别是120°F至150°F。设备可在不到五分钟内干燥单板 。
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8.发明授权公开(公告)号：US06979615B2
公开(公告)日：2005-12-27
申请号：US10243405
申请日：2002-09-12
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8242
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.
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9.发明授权Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis 有权建立低电压系数和滞后的高精度模拟电容的创新方法公开(公告)号：US06706635B2
公开(公告)日：2004-03-16
申请号：US10163450
申请日：2002-06-05
申请人： Imran M. Khan , William E. Nehrer , James Todd , Weidong Tian , Louis N. Hutter
发明人： Imran M. Khan , William E. Nehrer , James Todd , Weidong Tian , Louis N. Hutter
IPC分类号： H01L21302
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/76838 , H01L27/0805
摘要： The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.
摘要翻译： 本发明涉及一种在半导体衬底上形成anlog电容器的方法。 该方法包括在衬底的一部分上形成场氧化物，并在场氧化物层上形成多晶硅层，随后在多晶硅层上形成硅化物。 在衬底上形成第一层间电介质层，形成电容器屏蔽图案。 使用电容器掩模图案作为掩模蚀刻第一层间电介质，并且将硅化物层作为蚀刻停止层，并在衬底上形成薄的电介质。 在衬底上形成接触掩模图案，并且使用硅化物和衬底作为蚀刻停止层，在薄电介质和第一层间电介质上进行随后的蚀刻。 金属层沉积在衬底上，随后被平坦化，从而限定模拟电容器。
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