公开(公告)号：US06897518B1

公开(公告)日：2005-05-24

申请号：US10618191

申请日：2003-07-10

申请人： Sheung Hee Park ,  Richard M. Fastow ,  Dong-Hyuk Ju

发明人： Sheung Hee Park ,  Richard M. Fastow ,  Dong-Hyuk Ju

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A flash memory cell of the present invention comprises a floating gate, having a charge trapping region and a fin region. A source region and a drain region is formed proximate the floating gate. A control gate is formed above the charge trapping region of the floating gate. The fin region advantageously reduces leakage current, thereby allowing further scaling of the cell.

摘要翻译： 本发明的闪存单元包括具有电荷捕获区和鳍区的浮栅。 源极区域和漏极区域形成在浮动栅极附近。 控制栅极形成在浮置栅极的电荷俘获区域的上方。 翅片区域有利地减少泄漏电流，从而允许电池进一步缩放。

公开(公告)号：US08530977B1

公开(公告)日：2013-09-10

申请号：US10609159

申请日：2003-06-27

申请人： Imran Khan ,  Richard M. Fastow ,  Dong-Hyuk Ju

发明人： Imran Khan ,  Richard M. Fastow ,  Dong-Hyuk Ju

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7835

摘要： A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.

摘要翻译： 具有源极穿通保护植入物的金属氧化物半导体场效应晶体管（MOSFET）。 具体地，MOSFET包括半导体衬底，形成在半导体衬底上的栅极堆叠，源极和漏极区域以及保护注入。 半导体衬底包括第一p型掺杂浓度。 源极和漏极区域包括n型掺杂浓度，并且形成在半导体衬底中的栅极堆叠的相对侧上。 保护注入包括第二p型掺杂浓度，并且形成在源极区域下方的半导体衬底中并且围绕源极区域以保护源极区域与对应于漏极区域的耗尽区域保护。

公开(公告)号：US08536011B2

公开(公告)日：2013-09-17

申请号：US13074836

申请日：2011-03-29

申请人： Shibly S. Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

发明人： Shibly S. Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L29/788

CPC分类号： H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7885 ,  H01L29/792

摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

摘要翻译： 存储器件包括衬底和形成在衬底中的源区和漏区。 源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。 存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

公开(公告)号：US20120228704A1

公开(公告)日：2012-09-13

申请号：US13041512

申请日：2011-03-07

申请人： Dong-Hyuk Ju

发明人： Dong-Hyuk Ju

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0878 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66689 ,  H01L29/7816

摘要： A high-voltage transistor is formed in a deep well of a first conductivity type that has been formed in a semiconductor substrate or epitaxial layer of a second conductivity type. A body region of the second conductivity type is formed in the deep well, into which a source region of the first conductivity type is formed. A drain region of the first conductivity type is formed in the deep well and separated from the body region by a drift region in the deep well. A gate dielectric layer is formed over the body region, and a first polysilicon layer formed over the gate dielectric layer embodies the gate of the transistor. The field plate dielectric layer is formed over the drift region after the gate has been formed. Finally, the field plate dielectric is covered by a second polysilicon layer having a field plate positioned over the field plate dielectric layer in the drift region.

摘要翻译： 高压晶体管形成在已经形成在半导体衬底或第二导电类型的外延层中的第一导电类型的深阱中。 第二导电类型的体区形成在深阱中，形成第一导电类型的源极区。 第一导电类型的漏极区域形成在深井中，并且通过深井中的漂移区域与身体区域分离。 栅极电介质层形成在体区上，并且形成在栅极电介质层上的第一多晶硅层体现晶体管的栅极。 在形成栅极之后，在漂移区上形成场板电介质层。 最后，场板电介质被第二多晶硅层覆盖，该第二多晶硅层具有位于漂移区中的场板电介质层上的场板。

公开(公告)号：US06713819B1

公开(公告)日：2004-03-30

申请号：US10118364

申请日：2002-04-08

申请人： William G. En ,  Dong-Hyuk Ju ,  Srinath Krishnan

发明人： William G. En ,  Dong-Hyuk Ju ,  Srinath Krishnan

IPC分类号： H01L2976

CPC分类号： H01L29/78609 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612

摘要： An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

摘要翻译： 一种以绝缘体半导体形式形成的集成电路。 集成电路包括设置在绝缘层上的半导体材料层，其中设置在基板上的绝缘层。 提供第一和第二MOSFET，使得第一MOSFET的源极和漏极中的一个被设置为邻近第二MOSFET的源极和漏极之一。 在半导体材料层中形成非晶区域并从半导体材料层的上表面延伸到隔离层。 非晶区域形成在第一MOSFET的源极和漏极之一的结晶部分和第二MOSFET的源极和漏极之一的结晶部分之间。

公开(公告)号：US06277698B1

公开(公告)日：2001-08-21

申请号：US09382580

申请日：1999-08-25

申请人： Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

发明人： Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/823842

摘要： A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.

摘要翻译： 通过在沉积栅极电极层之前形成电介质膜，半导体器件设置有具有大致矩形轮廓的栅电极。 对电介质膜进行图案化和蚀刻以形成具有由开放区域分开的矩形轮廓的区域。 然后沉积栅极电极层，然后平坦化以形成具有基本上矩形轮廓的栅电极。

公开(公告)号：US06229187B1

公开(公告)日：2001-05-08

申请号：US09420972

申请日：1999-10-20

申请人： Dong-Hyuk Ju

发明人： Dong-Hyuk Ju

IPC分类号： H01L2972

CPC分类号： H01L29/66636 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76264 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/78609

摘要： A silicon on insulator (SOI) wafer is formed with an unoxidized perforation in the insulating silicon dioxide buried oxide layer. A field effect transistor (FET) structure on the SOI wafer is located above the unoxidized perforation such that the unoxidized perforation provides for electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the FET includes masking a silicon wafer prior to an oxygen implantation process to form the unoxidized perforated buried oxide layer in the wafer.

摘要翻译： 绝缘体上硅（SOI）晶片在绝缘二氧化硅掩埋氧化物层中形成有未氧化的穿孔。 SOI晶片上的场效应晶体管（FET）结构位于未氧化穿孔之上，使得未氧化的穿孔提供FET的通道区域与体硅衬底之间的电耦合，以消除由电荷积累引起的浮体效应 由于FET的历史操作导致的通道区域。 形成FET的方法包括在氧注入工艺之前掩蔽硅晶片以在晶片中形成未氧化的穿孔掩埋氧化物层。

公开(公告)号：US06008099A

公开(公告)日：1999-12-28

申请号：US50689

申请日：1998-03-30

申请人： Akif Sultan ,  Dong-Hyuk Ju

发明人： Akif Sultan ,  Dong-Hyuk Ju

IPC分类号： H01L21/265 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586

摘要： A method of making a lightly doped drain transistor includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and forming a drain (70) in a drain region (58) and a source (72) in a source region (60) of the substrate (56). The method further includes generating interstitials (62) near a lateral edge of at least one of the drain (70) and the source (72) and thermally treating the substrate (56). The thermal treatment cause the interstitials (62) to enhance a lateral diffusion (84) of the drain (70) under the gate oxide (54) without substantially impacting a vertical diffusion (82) of the drain (70) or the source (72). The enhanced lateral diffusion (84) results in the formation of at least one of a lightly doped drain extension region (75) and a lightly doped source extension region (76) without an increase in a junction depth of the drain (70) or the source (72). The step of generating interstitials (62) may include the step of implanting at least one of the drain region (58) and the source region (60) of the substrate (56) with a large tilt angle implant which creates the interstitials (62) at a location near the gate oxide (54).

摘要翻译： 一种制造轻掺杂漏极晶体管的方法包括以下步骤：在半导体衬底（56）上形成栅电极（52）和栅极氧化物（54），并在漏区（58）中形成漏极（70） 源极（72）在衬底（56）的源极区（60）中。 所述方法还包括在所述排水口（70）和所述源（72）中的至少一个的侧边缘附近产生间隙（62）并热处理所述衬底（56）。 热处理使间隙（62）增强栅极氧化物（54）下面的漏极（70）的横向扩散（84），而基本上不影响漏极（70）或源极（72）的垂直扩散（82） ）。 增强的横向扩散（84）导致轻掺杂漏极延伸区域（75）和轻掺杂源极延伸区域（76）中的至少一个的形成，而不会增加漏极（70）或 来源（72）。 产生间隙（62）的步骤可以包括用产生间隙（62）的大倾斜角植入物植入衬底（56）的漏区（58）和源区（60）中的至少一个的步骤， 在栅极氧化物（54）附近。

公开(公告)号：US08912014B1

公开(公告)日：2014-12-16

申请号：US11333208

申请日：2006-01-18

申请人： Chuan Lin ,  Dong-Hyuk Ju ,  Imran Khan ,  Jun Kang ,  Shibly S. Ahmed

发明人： Chuan Lin ,  Dong-Hyuk Ju ,  Imran Khan ,  Jun Kang ,  Shibly S. Ahmed

IPC分类号： H01L21/66

CPC分类号： G01R31/27 ,  G01R31/2884 ,  H01L22/12 ,  H01L22/34 ,  H01L27/0921

摘要： A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.

摘要翻译： 一种方法包括在源极区域或漏极区域中的至少一个与阱接触区域之间改变间隔以产生一组构型。 该方法还包括确定闭锁对每个配置的影响。

公开(公告)号：US07253068B1

公开(公告)日：2007-08-07

申请号：US10834095

申请日：2004-04-29

申请人： Dong-Hyuk Ju ,  Srinath Krishnan ,  Mario Pelella

发明人： Dong-Hyuk Ju ,  Srinath Krishnan ,  Mario Pelella

IPC分类号： H01L21/331

CPC分类号： H01L29/7841 ,  H01L21/76264 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.

摘要翻译： 绝缘体上硅（SOI）布置提供用于体电阻控制的双重SOI膜厚度，并提供其上提供掩埋氧化物（BOX）层的体硅衬底。 BOX层具有形成在其中的凹部和未加工的部分。 硅层形成在BOX层上，封闭凹槽并覆盖BOX层的未加工部分。 浅沟槽隔离区域限定并隔离第一硅区域与第二硅区域，每个硅区域包括凹陷之一。 浮动体装置形成在第一硅区域内，其呈现第一厚度，并且在第二硅区域内形成体系绑定的装置，该第二硅区域包括较厚的凹槽硅。