公开(公告)号：US20110215378A1

公开(公告)日：2011-09-08

申请号：US12929492

申请日：2011-01-28

申请人： In-Jun Hwang ,  Jong-Seob Kim ,  Hyuk-Soon Choi ,  Ki-Ha Hong ,  Jai-Kwang Shin ,  Jae-Joon Oh

发明人： In-Jun Hwang ,  Jong-Seob Kim ,  Hyuk-Soon Choi ,  Ki-Ha Hong ,  Jai-Kwang Shin ,  Jae-Joon Oh

IPC分类号： H01L29/778

CPC分类号： H01L29/66462 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/7783 ,  H01L29/7786

摘要： High electron mobility transistors (HEMT) exhibiting dual depletion and methods of manufacturing the same. The HEMT includes a source electrode, a gate electrode and a drain electrode disposed on a plurality of semiconductor layers having different polarities. A dual depletion region exists between the source electrode and the drain electrode. The plurality of semiconductor layers includes an upper material layer, an intermediate material layer and a lower material layer, and a polarity of the intermediate material layer is different from polarities of the upper material layer and the lower material layer.

摘要翻译： 表现出双重缺陷的高电子迁移率晶体管（HEMT）及其制造方法。 HEMT包括设置在具有不同极性的多个半导体层上的源电极，栅极电极和漏电极。 在源电极和漏电极之间存在双耗尽区。 多个半导体层包括上材料层，中间材料层和下材料层，并且中间材料层的极性与上材料层和下材料层的极性不同。

公开(公告)号：US20100271112A1

公开(公告)日：2010-10-28

申请号：US12742221

申请日：2008-11-04

申请人： Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

发明人： Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

IPC分类号： H03K3/01 ,  H01L29/78

CPC分类号： H01L29/66984 ,  B82Y25/00 ,  H01F1/401 ,  H01F1/404 ,  H01F10/1933 ,  H01F10/1936 ,  H01F10/3254 ,  H01F10/3295 ,  H01L29/82

摘要： Disclosed are a spin transistor and a method of operating the spin transistor. The disclosed spin transistor includes a channel formed of a magnetic material selectively passing a spin-polarized electron having a specific direction, a source formed of a magnetic material, a drain, and a gate electrode. When a predetermined voltage is applied to the gate electrode, the channel selectively passes a spin-polarized electron having a specific direction and thus, the spin transistor is selectively turned on.

摘要翻译： 公开了自旋晶体管和操作自旋晶体管的方法。 所公开的自旋晶体管包括由选择性地通过具有特定方向的自旋极化电子的磁性材料形成的沟道，由磁性材料形成的源极，漏极和栅电极。 当预定电压施加到栅电极时，沟道选择性地通过具有特定方向的自旋极化电子，因此自旋晶体管选择性地导通。

公开(公告)号：US08269293B2

公开(公告)日：2012-09-18

申请号：US12742221

申请日：2008-11-04

申请人： Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

发明人： Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

IPC分类号： H01L29/82

CPC分类号： H01L29/66984 ,  B82Y25/00 ,  H01F1/401 ,  H01F1/404 ,  H01F10/1933 ,  H01F10/1936 ,  H01F10/3254 ,  H01F10/3295 ,  H01L29/82

摘要： Disclosed are a spin transistor and a method of operating the spin transistor. The disclosed spin transistor includes a channel formed of a magnetic material selectively passing a spin-polarized electron having a specific direction, a source formed of a magnetic material, a drain, and a gate electrode. When a predetermined voltage is applied to the gate electrode, the channel selectively passes a spin-polarized electron having a specific direction and thus, the spin transistor is selectively turned on.

摘要翻译： 公开了自旋晶体管和操作自旋晶体管的方法。 所公开的自旋晶体管包括由选择性地通过具有特定方向的自旋极化电子的磁性材料形成的沟道，由磁性材料形成的源极，漏极和栅电极。 当预定电压施加到栅电极时，沟道选择性地通过具有特定方向的自旋极化电子，因此自旋晶体管选择性地导通。

公开(公告)号：US07829937B2

公开(公告)日：2010-11-09

申请号：US11980351

申请日：2007-10-31

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

公开(公告)号：US08119480B2

公开(公告)日：2012-02-21

申请号：US12923593

申请日：2010-09-29

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

公开(公告)号：US20110021014A1

公开(公告)日：2011-01-27

申请号：US12923593

申请日：2010-09-29

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

公开(公告)号：US20080164510A1

公开(公告)日：2008-07-10

申请号：US11980351

申请日：2007-10-31

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。