公开(公告)号：US20100271112A1

公开(公告)日：2010-10-28

申请号：US12742221

申请日：2008-11-04

申请人： Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

发明人： Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

IPC分类号： H03K3/01 ,  H01L29/78

CPC分类号： H01L29/66984 ,  B82Y25/00 ,  H01F1/401 ,  H01F1/404 ,  H01F10/1933 ,  H01F10/1936 ,  H01F10/3254 ,  H01F10/3295 ,  H01L29/82

摘要： Disclosed are a spin transistor and a method of operating the spin transistor. The disclosed spin transistor includes a channel formed of a magnetic material selectively passing a spin-polarized electron having a specific direction, a source formed of a magnetic material, a drain, and a gate electrode. When a predetermined voltage is applied to the gate electrode, the channel selectively passes a spin-polarized electron having a specific direction and thus, the spin transistor is selectively turned on.

摘要翻译： 公开了自旋晶体管和操作自旋晶体管的方法。 所公开的自旋晶体管包括由选择性地通过具有特定方向的自旋极化电子的磁性材料形成的沟道，由磁性材料形成的源极，漏极和栅电极。 当预定电压施加到栅电极时，沟道选择性地通过具有特定方向的自旋极化电子，因此自旋晶体管选择性地导通。

公开(公告)号：US08269293B2

公开(公告)日：2012-09-18

申请号：US12742221

申请日：2008-11-04

申请人： Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

发明人： Ki-Ha Hong ,  Sung-Hoon Lee ,  Jong-Seob Kim ,  Jai-Kwang Shin

IPC分类号： H01L29/82

CPC分类号： H01L29/66984 ,  B82Y25/00 ,  H01F1/401 ,  H01F1/404 ,  H01F10/1933 ,  H01F10/1936 ,  H01F10/3254 ,  H01F10/3295 ,  H01L29/82

摘要： Disclosed are a spin transistor and a method of operating the spin transistor. The disclosed spin transistor includes a channel formed of a magnetic material selectively passing a spin-polarized electron having a specific direction, a source formed of a magnetic material, a drain, and a gate electrode. When a predetermined voltage is applied to the gate electrode, the channel selectively passes a spin-polarized electron having a specific direction and thus, the spin transistor is selectively turned on.

摘要翻译： 公开了自旋晶体管和操作自旋晶体管的方法。 所公开的自旋晶体管包括由选择性地通过具有特定方向的自旋极化电子的磁性材料形成的沟道，由磁性材料形成的源极，漏极和栅电极。 当预定电压施加到栅电极时，沟道选择性地通过具有特定方向的自旋极化电子，因此自旋晶体管选择性地导通。

公开(公告)号：US07829937B2

公开(公告)日：2010-11-09

申请号：US11980351

申请日：2007-10-31

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

公开(公告)号：US08119480B2

公开(公告)日：2012-02-21

申请号：US12923593

申请日：2010-09-29

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

公开(公告)号：US20110021014A1

公开(公告)日：2011-01-27

申请号：US12923593

申请日：2010-09-29

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

公开(公告)号：US07787302B2

公开(公告)日：2010-08-31

申请号：US12073681

申请日：2008-03-07

申请人： Sung-Il Park ,  Sung-Hoon Lee ,  Kwang-Soo Seol ,  Young-Gu Jin ,  Jong-Seob Kim

发明人： Sung-Il Park ,  Sung-Hoon Lee ,  Kwang-Soo Seol ,  Young-Gu Jin ,  Jong-Seob Kim

IPC分类号： G11C16/04

CPC分类号： H01L21/28282 ,  G11C16/349 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792

摘要： Provided are a memory device, a method of manufacturing the same, and a method of operating the same. The memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected thereinto in a program or erase voltage such that the curved portions into which the charges are injected are separate from a portion which determines a threshold voltage, and a gate structure on the channel region.

摘要翻译： 提供了一种存储器件及其制造方法及其操作方法。 存储器件可以包括具有上端的上端弯曲的上端的通道区域，两侧的弯曲部分允许以编程或擦除电压将电荷注入其中，使得电荷的弯曲部分 注入与确定阈值电压的部分和沟道区上的栅极结构分开。

公开(公告)号：US20080285353A1

公开(公告)日：2008-11-20

申请号：US12073681

申请日：2008-03-07

申请人： Sung-II Park ,  Sung-Hoon Lee ,  Kwang-Soo Seol ,  Young-Gu Jin ,  Jong-Seob Kim

发明人： Sung-II Park ,  Sung-Hoon Lee ,  Kwang-Soo Seol ,  Young-Gu Jin ,  Jong-Seob Kim

IPC分类号： G11C16/06 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28282 ,  G11C16/349 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792

摘要： Provided are a memory device, a method of manufacturing the same, and a method of operating the same. The memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected thereinto in a program or erase voltage such that the curved portions into which the charges are injected are separate from a portion which determines a threshold voltage, and a gate structure on the channel region.

摘要翻译： 提供了一种存储器件及其制造方法及其操作方法。 存储器件可以包括具有上端的上端弯曲的上端的通道区域，两侧的弯曲部分允许以编程或擦除电压将电荷注入其中，使得电荷的弯曲部分 注入与确定阈值电压的部分和沟道区上的栅极结构分开。

公开(公告)号：US20080164510A1

公开(公告)日：2008-07-10

申请号：US11980351

申请日：2007-10-31

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

公开(公告)号：US09343756B2

公开(公告)日：2016-05-17

申请号：US12067086

申请日：2007-05-23

申请人： Sung-Jin Oh ,  Kyoung-Hwang Lee ,  Seung-Ho Baek ,  Sung-Hoon Lee ,  Il-Tae Park ,  Byung-Sun Hong ,  Mee-Nam Shinn

发明人： Sung-Jin Oh ,  Kyoung-Hwang Lee ,  Seung-Ho Baek ,  Sung-Hoon Lee ,  Il-Tae Park ,  Byung-Sun Hong ,  Mee-Nam Shinn

IPC分类号： H01M8/04 ,  H01M8/02 ,  H01M8/24 ,  H01M8/10

CPC分类号： H01M8/0263 ,  H01M8/0258 ,  H01M8/0267 ,  H01M8/04029 ,  H01M8/04067 ,  H01M8/04089 ,  H01M8/04201 ,  H01M8/04529 ,  H01M8/04679 ,  H01M8/04753 ,  H01M8/1004 ,  H01M8/1039 ,  H01M8/241 ,  H01M8/2457 ,  H01M8/2483 ,  H01M8/2484 ,  H01M8/2485 ,  H01M2008/1095 ,  H01M2300/0082 ,  Y02E60/50

摘要： A fuel cell separator, a fuel cell stack having the fuel cell separator, and a reactant gas control method of the fuel cell stack are provided. That is, even when the fuel cell stack operates under the low load operation condition, a reactant gas is supplied to the reactant gas passages of the fuel cell separator, and thus, the length of the passage can be shortened by 50% as compared with the prior art having only one reactant gas passage. Therefore, the reactant gas can be effectively supplied without experiencing pressure loss. Further, in the high load operation of the fuel cell stack, the reactant gas is introduced into the first reactant gas passage of the fuel cell separator and utilized in half of the whole electrode area. Subsequently, the reactant gas is introduced into the second reactant gas passage and utilized in the remaining half of the electrode area. The flow rate of the reactant gas flowing along the passage channels is increased by two times, even when the reactant gas utilizing rate is identical as compared with the reactant gas flow in the low load operation. As a result, the moisture existing in the passage channels can be more effectively discharged and the flooding phenomenon occurring in the high load operation can be prevented. By controlling the reactant gas supply in accordance with an operation condition of the fuel cell stack without experiencing pressure loss and deterioration of the utilizing rate, the flooding phenomenon and concentration polarization phenomenon that occur in the fuel cell stack can be prevented.

摘要翻译： 提供燃料电池隔板，具有燃料电池隔板的燃料电池堆和燃料电池堆的反应气体控制方法。 也就是说，即使燃料电池堆在低负载运转条件下运转，向燃料电池用隔板的反应气体通路供给反应气体，因此与通常的通路长度相比可以缩短50％ 现有技术仅具有一个反应气体通道。 因此，能够有效地供给反应气体而不会发生压力损失。 此外，在燃料电池堆的高负荷运转中，将反应气体导入燃料电池用隔板的第一反应气体通路，并用于整个电极区域的一半。 随后，反应气体被引入到第二反应气体通道中，并用于电极区域的剩余部分。 即使反应物气体的利用率与低负荷运转中的反应气体流量相同，流过通道的反应气体的流量增加了两倍。 结果，可以更有效地排出存在于通道通道中的水分，并且可以防止在高负载操作中发生的溢流现象。 通过根据燃料电池堆的操作条件控制反应气体的供给而不会发生压力损失和利用率的劣化，可以防止在燃料电池堆中发生的溢流现象和浓缩极化现象。

公开(公告)号：US08166230B2

公开(公告)日：2012-04-24

申请号：US12353403

申请日：2009-01-14

申请人： Jin-Hyeok Choi ,  Sung-Hoon Lee ,  Si-Hoon Hong ,  Tae-Keun Jeon

发明人： Jin-Hyeok Choi ,  Sung-Hoon Lee ,  Si-Hoon Hong ,  Tae-Keun Jeon

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F9/00

CPC分类号： G06F12/0646

摘要： A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

摘要翻译： 提供了一种存储器系统，包括主处理器和连接到主处理器的多个级联连接的存储卡。 每个存储卡在存储器系统的初始化之前存储相同的默认相对卡地址（RCA）。 主处理器配置为使用默认RCA顺序访问每个存储卡，并且在每次顺序访问时将默认RCA更改为唯一的RCA。