公开(公告)号：US07571203B2

公开(公告)日：2009-08-04

申请号：US10972235

申请日：2004-10-21

申请人： In-San Jeon ,  Hyuk Kim ,  Jae-Seok Kim ,  Kyung-Soo Kim ,  Hee-Bum Jung ,  Jong-Dae Kim

发明人： In-San Jeon ,  Hyuk Kim ,  Jae-Seok Kim ,  Kyung-Soo Kim ,  Hee-Bum Jung ,  Jong-Dae Kim

IPC分类号： G06F7/32

CPC分类号： H04L1/0656 ,  G06F17/16 ,  H04L25/0242

摘要： Disclosed is a V-BLAST system for a MIMO communication system.In the V-BLAST system for a MIMO communication system, a pseudo inverse matrix calculator receives a channel transfer function matrix including channel information and produces a cofactor matrix and a determinant for a pseudo inverse matrix. A norm & minimum calculator calculates a minimum index for the cofactor matrix outputted from the pseudo inverse matrix calculator, a weight vector selector selects a row vector having the minimum index and calculates a transposed matrix for the row vector; an adder adds the transposed matrix to a received input symbol, and a subtractor subtracts the determinant to the output. A demapper performs a determined function operation to the output and produces estimated information.

摘要翻译： 公开了一种用于MIMO通信系统的V-BLAST系统。 在用于MIMO通信系统的V-BLAST系统中，伪逆矩阵计算器接收包括信道信息的信道传递函数矩阵，并产生用于伪逆矩阵的辅因子矩阵和行列式。 规范和最小计算器计算从伪逆矩阵计算器输出的辅因子矩阵的最小索引，权重向量选择器选择具有最小索引的行向量并计算行向量的转置矩阵; 加法器将转置的矩阵添加到接收到的输入符号，并且减法器将输出的行列式减去。 解映射器对输出执行确定的功能操作并产生估计信息。

公开(公告)号：US20050149596A1

公开(公告)日：2005-07-07

申请号：US10972235

申请日：2004-10-21

申请人： In-San Jeon ,  Hyuk Kim ,  Jae-Seok Kim ,  Kyung-Soo Kim ,  Hee-Bum Jung ,  Jong-Dae Kim

发明人： In-San Jeon ,  Hyuk Kim ,  Jae-Seok Kim ,  Kyung-Soo Kim ,  Hee-Bum Jung ,  Jong-Dae Kim

IPC分类号： H04B7/02 ,  G06F17/10 ,  G06F17/16 ,  H04L1/06 ,  H04L25/02

CPC分类号： H04L1/0656 ,  G06F17/16 ,  H04L25/0242

摘要： Disclosed is a V-BLAST system for a MIMO communication system. In the V-BLAST system for a MIMO communication system, a pseudo inverse matrix calculator receives a channel transfer function matrix including channel information and produces a cofactor matrix and a determinant for a pseudo inverse matrix. A norm & minimum calculator calculates a minimum index for the cofactor matrix outputted from the pseudo inverse matrix calculator, a weight vector selector selects a row vector having the minimum index and calculates a transposed matrix for the row vector; an adder adds the transposed matrix to a received input symbol, and a subtractor subtracts the determinant to the output. A demapper performs a determined function operation to the output and produces estimated information.

摘要翻译： 公开了一种用于MIMO通信系统的V-BLAST系统。 在用于MIMO通信系统的V-BLAST系统中，伪逆矩阵计算器接收包括信道信息的信道传递函数矩阵，并产生用于伪逆矩阵的辅因子矩阵和行列式。 规范和最小计算器计算从伪逆矩阵计算器输出的辅因子矩阵的最小索引，权重向量选择器选择具有最小索引的行向量并计算行向量的转置矩阵; 加法器将转置的矩阵添加到接收到的输入符号，并且减法器将输出的行列式减去。 解映射器对输出执行确定的功能操作并产生估计信息。

公开(公告)号：US20060136802A1

公开(公告)日：2006-06-22

申请号：US11263443

申请日：2005-10-31

申请人： In-San Jeon ,  Hyuk Kim ,  Kyung-Soo Kim ,  Ik-Soo Eo ,  Hee-Bum Jung

发明人： In-San Jeon ,  Hyuk Kim ,  Kyung-Soo Kim ,  Ik-Soo Eo ,  Hee-Bum Jung

IPC分类号： H03M13/03

CPC分类号： H03M13/395 ,  H03M13/4107 ,  H03M13/4192

摘要： A hybrid trace back apparatus and a high-speed Viterbi decoding system having the same are disclosed. The hybrid trace back apparatus includes: a register exchanging unit for receiving survivor values of each states from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation; a first storing unit for the register exchange operation; a second storing unit for storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory; and a block trace back unit for outputting decoded data by performing a block trace back operation while writing a value of the second storing unit.

公开(公告)号：US07530010B2

公开(公告)日：2009-05-05

申请号：US11263443

申请日：2005-10-31

申请人： In-San Jeon ,  Hyuk Kim ,  Kyung-Soo Kim ,  Ik-Soo Eo ,  Hee-Bum Jung

发明人： In-San Jeon ,  Hyuk Kim ,  Kyung-Soo Kim ,  Ik-Soo Eo ,  Hee-Bum Jung

IPC分类号： H03M13/03

CPC分类号： H03M13/395 ,  H03M13/4107 ,  H03M13/4192

摘要： A hybrid trace back apparatus and a high-speed Viterbi decoding system having the same are disclosed. The hybrid trace back apparatus includes: a register exchanging unit for receiving survivor values of each states from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation; a first storing unit for the register exchange operation; a second storing unit for storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory; and a block trace back unit for outputting decoded data by performing a block trace back operation while writing a value of the second storing unit.

摘要翻译： 公开了具有该混合追溯装置和高速维特比解码系统。 混合追溯装置包括：寄存器交换单元，用于从路径度量计算器接收每个状态的幸存值，并通过寄存器交换操作获得块存活值，作为块追溯操作的位长; 用于寄存器交换操作的第一存储单元; 第二存储单元，用于存储通过寄存器交换操作获得的块存活值，直到块存储值被写入块追溯存储器; 以及块追溯单元，用于通过在写入第二存储单元的值的同时执行块追溯操作来输出解码数据。

公开(公告)号：US06772389B2

公开(公告)日：2004-08-03

申请号：US09966201

申请日：2001-09-26

申请人： Hyuk Kim ,  In-San Jeon ,  Woo-Seok Yang ,  Kyung-Soo Kim ,  Han-Jin Cho

发明人： Hyuk Kim ,  In-San Jeon ,  Woo-Seok Yang ,  Kyung-Soo Kim ,  Han-Jin Cho

IPC分类号： H03M1345

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3927 ,  H03M13/6502 ,  H03M13/6577

摘要： Disclosed are a turbo decoder, which applies a base-2 binary LogMAP algorithm in implementing a turbo decoder to thereby reduce the hardware requirement and implement a high-speed turbo decoder, which comprising a split for splitting the sum of two input state metrics into an integral and a decimal part; a comparator for comparing the integral parts of the two state metrics to extract a maximum and a minimum integer; a subtractor for obtaining a difference between the original integral part and the maximum or minimum integer value; a lookup table for calculating the sum of exponential terms of base-2 function in the decimal parts; a shifter for shifting only a decimal part with a smaller integral part by the difference; an adder for adding the decimal part and a decimal part with a larger integral part; a log pre-processing block for applying a base-2 logarithm on the decimal part to thereby obtain a final value for the decimal part; and an adder for adding the maximum integral value and the final value for the decimal part to thereby obtain a final value of the base-2 function.

摘要翻译： 公开了一种turbo解码器，其在实现turbo解码器中应用基2二进制LogMAP算法，从而降低硬件要求并实现高速turbo解码器，该高速turbo解码器包括用于将两个输入状态度量的和分解为 积分和小数部分; 用于比较两个状态度量的积分部分以提取最大和最小整数的比较器; 用于获得原始积分部分与最大或最小整数值之间的差的减法器; 用于计算小数部分中base-2函数的指数项的和的查找表; 移位器，用于仅移动具有较小整数部分的小数部分的差值; 用于将小数部分和小数部分与较大整数部分相加的加法器; 用于在小数部分应用基2对数的日志预处理块，从而获得小数部分的最终值; 以及加法器，用于将最大积分值和小数部分的最终值相加，从而获得基2功能的最终值。

公开(公告)号：US5727029A

公开(公告)日：1998-03-10

申请号：US575076

申请日：1995-12-19

申请人： In-San Jeon ,  Ik-Su Eo ,  In-Ki Lim ,  Kwang-Il Yeon ,  Jae-Seok Kim

发明人： In-San Jeon ,  Ik-Su Eo ,  In-Ki Lim ,  Kwang-Il Yeon ,  Jae-Seok Kim

IPC分类号： H03M13/00 ,  H03M13/41 ,  H04L1/00 ,  H03D1/00 ,  H04L27/06

CPC分类号： H03M13/3961 ,  H03M13/4107 ,  H04L1/0054

摘要： The present invention relates in general to a channel CODEC to increase the transmitting effect on a communication channel of a communication system, and more specifically to a branch metric module of a viterbi decoder. The module includes an operator for operating and outputting the differential magnitude of two signals, one signal being a code word generated to perform the viterbi decode and the other being a signal transmitted through the channel. An adder sums and outputs the data which is outputted to it from the operator. A receiving code word converter converts the magnitude of any of bits by the linear sampling quantization process, and non-linearly converts it in accordance with a preestimated or predetermined format. A number of operators calculate the magnitude between two signals at the absolute value to convert the magnitude of an inputted generative code word and the magnitude of the non-linear converted receiving code word. The adder sums and outputs the result to a branch metric converter, which converts the output according to the preestimated format.

摘要翻译： 本发明一般涉及增加对通信系统的通信信道的传输效果的信道CODEC，更具体地涉及维特比解码器的分支量度模块。 该模块包括用于操作和输出两个信号的差分幅度的操作器，一个信号是被执行维特比解码而产生的代码字，另一个是通过该信道发送的信号。 加法器对从操作者向其输出的数据进行求和并输出。 接收码字转换器通过线性采样量化处理来转换任何位的幅度，并且根据预先预定的格式非线性地转换它。 许多算子以绝对值计算两个信号之间的幅度，以转换输入的生成码字的大小和非线性转换的接收码字的大小。 加法器将结果相加并输出到分支度量转换器，该转换器根据预先预定的格式转换输出。