公开(公告)号：US07571203B2

公开(公告)日：2009-08-04

申请号：US10972235

申请日：2004-10-21

申请人： In-San Jeon ,  Hyuk Kim ,  Jae-Seok Kim ,  Kyung-Soo Kim ,  Hee-Bum Jung ,  Jong-Dae Kim

发明人： In-San Jeon ,  Hyuk Kim ,  Jae-Seok Kim ,  Kyung-Soo Kim ,  Hee-Bum Jung ,  Jong-Dae Kim

IPC分类号： G06F7/32

CPC分类号： H04L1/0656 ,  G06F17/16 ,  H04L25/0242

摘要： Disclosed is a V-BLAST system for a MIMO communication system.In the V-BLAST system for a MIMO communication system, a pseudo inverse matrix calculator receives a channel transfer function matrix including channel information and produces a cofactor matrix and a determinant for a pseudo inverse matrix. A norm & minimum calculator calculates a minimum index for the cofactor matrix outputted from the pseudo inverse matrix calculator, a weight vector selector selects a row vector having the minimum index and calculates a transposed matrix for the row vector; an adder adds the transposed matrix to a received input symbol, and a subtractor subtracts the determinant to the output. A demapper performs a determined function operation to the output and produces estimated information.

摘要翻译： 公开了一种用于MIMO通信系统的V-BLAST系统。 在用于MIMO通信系统的V-BLAST系统中，伪逆矩阵计算器接收包括信道信息的信道传递函数矩阵，并产生用于伪逆矩阵的辅因子矩阵和行列式。 规范和最小计算器计算从伪逆矩阵计算器输出的辅因子矩阵的最小索引，权重向量选择器选择具有最小索引的行向量并计算行向量的转置矩阵; 加法器将转置的矩阵添加到接收到的输入符号，并且减法器将输出的行列式减去。 解映射器对输出执行确定的功能操作并产生估计信息。

公开(公告)号：US20050149596A1

公开(公告)日：2005-07-07

申请号：US10972235

申请日：2004-10-21

申请人： In-San Jeon ,  Hyuk Kim ,  Jae-Seok Kim ,  Kyung-Soo Kim ,  Hee-Bum Jung ,  Jong-Dae Kim

发明人： In-San Jeon ,  Hyuk Kim ,  Jae-Seok Kim ,  Kyung-Soo Kim ,  Hee-Bum Jung ,  Jong-Dae Kim

IPC分类号： H04B7/02 ,  G06F17/10 ,  G06F17/16 ,  H04L1/06 ,  H04L25/02

CPC分类号： H04L1/0656 ,  G06F17/16 ,  H04L25/0242

摘要： Disclosed is a V-BLAST system for a MIMO communication system. In the V-BLAST system for a MIMO communication system, a pseudo inverse matrix calculator receives a channel transfer function matrix including channel information and produces a cofactor matrix and a determinant for a pseudo inverse matrix. A norm & minimum calculator calculates a minimum index for the cofactor matrix outputted from the pseudo inverse matrix calculator, a weight vector selector selects a row vector having the minimum index and calculates a transposed matrix for the row vector; an adder adds the transposed matrix to a received input symbol, and a subtractor subtracts the determinant to the output. A demapper performs a determined function operation to the output and produces estimated information.

摘要翻译： 公开了一种用于MIMO通信系统的V-BLAST系统。 在用于MIMO通信系统的V-BLAST系统中，伪逆矩阵计算器接收包括信道信息的信道传递函数矩阵，并产生用于伪逆矩阵的辅因子矩阵和行列式。 规范和最小计算器计算从伪逆矩阵计算器输出的辅因子矩阵的最小索引，权重向量选择器选择具有最小索引的行向量并计算行向量的转置矩阵; 加法器将转置的矩阵添加到接收到的输入符号，并且减法器将输出的行列式减去。 解映射器对输出执行确定的功能操作并产生估计信息。

公开(公告)号：US20060136802A1

公开(公告)日：2006-06-22

申请号：US11263443

申请日：2005-10-31

申请人： In-San Jeon ,  Hyuk Kim ,  Kyung-Soo Kim ,  Ik-Soo Eo ,  Hee-Bum Jung

发明人： In-San Jeon ,  Hyuk Kim ,  Kyung-Soo Kim ,  Ik-Soo Eo ,  Hee-Bum Jung

IPC分类号： H03M13/03

CPC分类号： H03M13/395 ,  H03M13/4107 ,  H03M13/4192

摘要： A hybrid trace back apparatus and a high-speed Viterbi decoding system having the same are disclosed. The hybrid trace back apparatus includes: a register exchanging unit for receiving survivor values of each states from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation; a first storing unit for the register exchange operation; a second storing unit for storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory; and a block trace back unit for outputting decoded data by performing a block trace back operation while writing a value of the second storing unit.

公开(公告)号：US07530010B2

公开(公告)日：2009-05-05

申请号：US11263443

申请日：2005-10-31

申请人： In-San Jeon ,  Hyuk Kim ,  Kyung-Soo Kim ,  Ik-Soo Eo ,  Hee-Bum Jung

发明人： In-San Jeon ,  Hyuk Kim ,  Kyung-Soo Kim ,  Ik-Soo Eo ,  Hee-Bum Jung

IPC分类号： H03M13/03

CPC分类号： H03M13/395 ,  H03M13/4107 ,  H03M13/4192

摘要： A hybrid trace back apparatus and a high-speed Viterbi decoding system having the same are disclosed. The hybrid trace back apparatus includes: a register exchanging unit for receiving survivor values of each states from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation; a first storing unit for the register exchange operation; a second storing unit for storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory; and a block trace back unit for outputting decoded data by performing a block trace back operation while writing a value of the second storing unit.

摘要翻译： 公开了具有该混合追溯装置和高速维特比解码系统。 混合追溯装置包括：寄存器交换单元，用于从路径度量计算器接收每个状态的幸存值，并通过寄存器交换操作获得块存活值，作为块追溯操作的位长; 用于寄存器交换操作的第一存储单元; 第二存储单元，用于存储通过寄存器交换操作获得的块存活值，直到块存储值被写入块追溯存储器; 以及块追溯单元，用于通过在写入第二存储单元的值的同时执行块追溯操作来输出解码数据。

公开(公告)号：US07020832B2

公开(公告)日：2006-03-28

申请号：US10039005

申请日：2001-12-31

申请人： In San Jeon ,  Hyuk Kim ,  Woo Seok Yang ,  Kyung Soo Kim ,  Whan Woo Kim ,  Han Jin Cho

发明人： In San Jeon ,  Hyuk Kim ,  Woo Seok Yang ,  Kyung Soo Kim ,  Whan Woo Kim ,  Han Jin Cho

IPC分类号： H03M13/03

CPC分类号： H03M13/3922 ,  H03M13/2957 ,  H03M13/6502 ,  H03M13/6505

摘要： The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

公开(公告)号：US06772389B2

公开(公告)日：2004-08-03

申请号：US09966201

申请日：2001-09-26

申请人： Hyuk Kim ,  In-San Jeon ,  Woo-Seok Yang ,  Kyung-Soo Kim ,  Han-Jin Cho

发明人： Hyuk Kim ,  In-San Jeon ,  Woo-Seok Yang ,  Kyung-Soo Kim ,  Han-Jin Cho

IPC分类号： H03M1345

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3927 ,  H03M13/6502 ,  H03M13/6577

摘要： Disclosed are a turbo decoder, which applies a base-2 binary LogMAP algorithm in implementing a turbo decoder to thereby reduce the hardware requirement and implement a high-speed turbo decoder, which comprising a split for splitting the sum of two input state metrics into an integral and a decimal part; a comparator for comparing the integral parts of the two state metrics to extract a maximum and a minimum integer; a subtractor for obtaining a difference between the original integral part and the maximum or minimum integer value; a lookup table for calculating the sum of exponential terms of base-2 function in the decimal parts; a shifter for shifting only a decimal part with a smaller integral part by the difference; an adder for adding the decimal part and a decimal part with a larger integral part; a log pre-processing block for applying a base-2 logarithm on the decimal part to thereby obtain a final value for the decimal part; and an adder for adding the maximum integral value and the final value for the decimal part to thereby obtain a final value of the base-2 function.

摘要翻译： 公开了一种turbo解码器，其在实现turbo解码器中应用基2二进制LogMAP算法，从而降低硬件要求并实现高速turbo解码器，该高速turbo解码器包括用于将两个输入状态度量的和分解为 积分和小数部分; 用于比较两个状态度量的积分部分以提取最大和最小整数的比较器; 用于获得原始积分部分与最大或最小整数值之间的差的减法器; 用于计算小数部分中base-2函数的指数项的和的查找表; 移位器，用于仅移动具有较小整数部分的小数部分的差值; 用于将小数部分和小数部分与较大整数部分相加的加法器; 用于在小数部分应用基2对数的日志预处理块，从而获得小数部分的最终值; 以及加法器，用于将最大积分值和小数部分的最终值相加，从而获得基2功能的最终值。

公开(公告)号：US20070237246A1

公开(公告)日：2007-10-11

申请号：US11496897

申请日：2006-08-01

申请人： In Gi Lim ,  Hyung Il Park ,  Young Seok Baek ,  Hyuk Kim ,  Tae Joon Kim ,  Kyung Soo Kim ,  Ik Soo Eo ,  Hee Bum Jung

发明人： In Gi Lim ,  Hyung Il Park ,  Young Seok Baek ,  Hyuk Kim ,  Tae Joon Kim ,  Kyung Soo Kim ,  Ik Soo Eo ,  Hee Bum Jung

IPC分类号： H04K1/10

CPC分类号： H04L27/2662 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0071 ,  H04L5/06 ,  H04L27/2657

摘要： A wireless modem is mounted to a terminal for wireless communication, and specifically controls an internal drive clock to reduce power consumption in an active mode. The wireless modem includes: a wireless core module for transmitting and receiving a radio signal; a modulator for converting data to be transmitted into a wireless transmission signal and transmitting the converted signal to the wireless core module; a demodulator for converting the signal received from the wireless core module into reception data; a synchronizer for synchronizing the signal received from the wireless core module; and a clock controller for generating a drive clock of each of the modulator, the demodulator, and the synchronizer. A low power clock controller is divided into six main functional blocks of a synchronizer, an analog controller, a modulator, a channel decoder, a demodulator, and a channel encoder, and has a feature that a clock is input only when a main functional block operates. As a result, it is possible to minimize power consumption caused by clock switching when an Orthogonal Frequency Division Multiplexing Access (OFDMA) mobile station modem operates in an active mode through the clock controller.

摘要翻译： 无线调制解调器被安装到用于无线通信的终端，并且具体地控制内部驱动时钟以降低活动模式中的功耗。 无线调制解调器包括：用于发送和接收无线电信号的无线核心模块; 用于将要发送的数据转换成无线发送信号并将转换的信号发送到无线核心模块的调制器; 解调器，用于将从无线核心模块接收的信号转换为接收数据; 用于使从所述无线核心模块接收的信号同步的同步器; 以及时钟控制器，用于产生调制器，解调器和同步器中的每一个的驱动时钟。 低功率时钟控制器被分为同步器，模拟控制器，调制器，信道解码器，解调器和信道编码器的六个主要功能块，并且具有仅当主功能块 操作。 结果，当正交频分复用接入（OFDMA）移动台调制解调器通过时钟控制器以活动模式操作时，可以最小化由时钟切换引起的功率消耗。

公开(公告)号：US08539325B2

公开(公告)日：2013-09-17

申请号：US12972289

申请日：2010-12-17

申请人： In San Jeon ,  Hyuk Kim ,  Han Jin Cho

发明人： In San Jeon ,  Hyuk Kim ,  Han Jin Cho

IPC分类号： G06F11/00

CPC分类号： H03M13/6525 ,  H03M13/2957 ,  H03M13/3922 ,  H03M13/3927

摘要： An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.

摘要翻译： 提供了一种用于生成用于turbo解码的奇偶校验位的装置，以及MAP（Maximum A Reareriori）装置。 用于生成用于turbo解码的奇偶校验位的装置包括：索引转换器，相对于奇偶校验位，通过根据信息比特和输入符号保持或改变正向和反向状态矩阵之间的关系来计算正向和反向状态矩阵 编码器状态; 以及奇偶校验计算单元，通过使用由奇偶校验状态矩阵计算单元计算的正向和反向状态矩阵来计算奇偶校验位。

公开(公告)号：US08583975B2

公开(公告)日：2013-11-12

申请号：US13270433

申请日：2011-10-11

申请人： Hyuk Kim ,  In San Jeon ,  Seong Min Kim ,  Bon Tae Koo

发明人： Hyuk Kim ,  In San Jeon ,  Seong Min Kim ,  Bon Tae Koo

IPC分类号： G08C25/02

CPC分类号： H04L1/1845 ,  H04L1/0066 ,  H04L1/1812 ,  H04L1/1819

摘要： A packet combining device for a communication system using hybrid automatic repeat request (HARQ) includes: a HARQ buffer; a combiner configured to combine data which is previously received and stored in the HARQ buffer with newly-received data; and a channel decoder configured to attempt channel decoding by using the combined received data provided from the combiner and provide one or more of log likelihood ratios (LLRs) computed for a systematic bit and a parity bit of the combined received data to the combiner such that the one or more LLRs are combined with the data used for channel decoding.

摘要翻译： 一种使用混合自动重传请求（HARQ）的通信系统的分组组合装置包括：HARQ缓冲器; 组合器，被配置为将先前接收并存储在HARQ缓冲器中的数据与新接收的数据组合; 以及信道解码器，被配置为通过使用从组合器提供的组合的接收数据来尝试信道解码，并且向组合器提供为组合接收数据计算的系统位和奇偶校验位的对数似然比（LLR）中的一个或多个， 一个或多个LLR与用于信道解码的数据组合。

公开(公告)号：US20110154149A1

公开(公告)日：2011-06-23

申请号：US12972289

申请日：2010-12-17

申请人： In San Jeon ,  Hyuk Kim ,  Han Jin Cho

发明人： In San Jeon ,  Hyuk Kim ,  Han Jin Cho

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/6525 ,  H03M13/2957 ,  H03M13/3922 ,  H03M13/3927

摘要： An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.

摘要翻译： 提供了一种用于生成用于turbo解码的奇偶校验位的装置，以及MAP（Maximum A Reareriori）装置。 用于生成用于turbo解码的奇偶校验位的装置包括：索引转换器，相对于奇偶校验位，通过根据信息比特和输入符号保持或改变正向和反向状态矩阵之间的关系来计算正向和反向状态矩阵 编码器状态; 以及奇偶校验计算单元，通过使用由奇偶校验状态矩阵计算单元计算的正向和反向状态矩阵来计算奇偶校验位。