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    Methods of manufacturing semiconductor devices having low resistance buried gate structures
    1.
    发明授权
    Methods of manufacturing semiconductor devices having low resistance buried gate structures 有权
    制造具有低电阻掩埋栅极结构的半导体器件的方法

    公开(公告)号：US08168521B2

    公开(公告)日：2012-05-01

    申请号：US12725743

    申请日：2010-03-17

    申请人： In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Ghun Shin ,  Suk-Hun Choi

    发明人： In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Ghun Shin ,  Suk-Hun Choi

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/4236 ,  H01L21/67207 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66621 ,  H01L29/78

    摘要： In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.

    摘要翻译： 在制造半导体器件的方法中，在衬底的有源区中形成凹部。 在第一凹部中形成栅极绝缘层。 在栅绝缘层上形成阻挡层。 在阻挡层上形成具有第一电阻的预成核层。 将初始成核层转变成具有比第一电阻显着小的第二电阻的成核层。 在成核层上形成导电层。 部分蚀刻导电层，成核层，势垒层和栅极绝缘层，以形成包括栅极绝缘层图案，势垒层图案，成核层图案和导电层图案的掩埋栅极结构。

    Methods of Manufacturing Semiconductor Devices Having Low Resistance Buried Gate Structures
    2.
    发明申请
    Methods of Manufacturing Semiconductor Devices Having Low Resistance Buried Gate Structures 有权
    制造具有低电阻掩埋栅极结构的半导体器件的方法

    公开(公告)号：US20100240180A1

    公开(公告)日：2010-09-23

    申请号：US12725743

    申请日：2010-03-17

    申请人： In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Gyun Shin ,  Suk-Hun Choi

    发明人： In-Sang Jeon ,  Si-Hyung Lee ,  Jong-Ryeol Yoo ,  Yu-Gyun Shin ,  Suk-Hun Choi

    IPC分类号： H01L21/336 ,  H01L21/8242

    CPC分类号： H01L29/4236 ,  H01L21/67207 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66621 ,  H01L29/78

    摘要： In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.

    摘要翻译： 在制造半导体器件的方法中，在衬底的有源区中形成凹部。 在第一凹部中形成栅极绝缘层。 在栅绝缘层上形成阻挡层。 在阻挡层上形成具有第一电阻的预成核层。 将初始成核层转变成具有比第一电阻显着小的第二电阻的成核层。 在成核层上形成导电层。 所述导电层，所述成核层，阻挡层和该栅极绝缘层被部分地蚀刻，以形成包括栅极绝缘层图案，阻挡层图案，一个成核层图案和导电层图案的埋入栅极结构。

    Non-volatile memory device and method of forming the same
    3.
    发明申请
    Non-volatile memory device and method of forming the same 审中-公开
    非易失性存储器件及其形成方法

    公开(公告)号：US20090134448A1

    公开(公告)日：2009-05-28

    申请号：US12230835

    申请日：2008-09-05

    申请人： Taek-Soo Jeon ,  Si-Young Choi ,  In-Sang Jeon ,  Sang-Bom Kang ,  Si-Hyung Lee ,  Seung-Hoon Hong

    发明人： Taek-Soo Jeon ,  Si-Young Choi ,  In-Sang Jeon ,  Sang-Bom Kang ,  Si-Hyung Lee ,  Seung-Hoon Hong

    IPC分类号： H01L29/68 ,  H01L21/336

    CPC分类号： H01L29/4234 ,  H01L29/40117

    摘要： Example embodiments provide a non-volatile semiconductor memory device and method of forming the same. The non-volatile memory device may include a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a first blocking insulation layer on the charge storage layer, and a gate electrode on the first blocking insulation layer, wherein the gate electrode includes aluminum and the first blocking insulation layer does not include aluminum.

    摘要翻译： 示例性实施例提供了一种非易失性半导体存储器件及其形成方法。 非易失性存储器件可以包括半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的第一阻挡绝缘层和第一阻挡绝缘层上的栅电极，其中 栅电极包括铝，并且第一阻挡绝缘层不包括铝。

    Recess gate transistor
    4.
    发明授权
    Recess gate transistor 有权
    凹槽门晶体管

    公开(公告)号：US08889539B2

    公开(公告)日：2014-11-18

    申请号：US12332877

    申请日：2008-12-11

    申请人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    发明人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    IPC分类号： H01L21/302 ,  H01L29/66 ,  H01L29/423

    CPC分类号： H01L29/4236 ,  H01L29/66621

    摘要： A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

    摘要翻译： 提供一种形成半导体器件的方法，包括：通过图案化绝缘层在衬底上形成多个硬掩模; 在衬底中形成多个沟槽，每个沟槽具有设置在两个相邻掩模之间并且从底部到上部垂直延伸的沟槽壁; 在硬掩模和沟槽壁上形成绝缘层; 在绝缘层上形成导电层; 蚀刻导电层以形成导电层图案以填充沟槽的底部; 在导电层图案和沟槽壁上沉积缓冲层; 以及用覆盖层填充沟槽的上部。

    Recess gate transistor
    6.
    发明授权
    Recess gate transistor 有权
    凹槽门晶体管

    公开(公告)号：US08012828B2

    公开(公告)日：2011-09-06

    申请号：US12251054

    申请日：2008-10-14

    申请人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

    发明人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66553 ,  H01L21/28079 ,  H01L21/28114 ,  H01L29/4236

    摘要： A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

    摘要翻译： 提供半导体器件的凹槽，其包括：形成有凹部的基板; 形成在所述凹部的底部的金属层; 形成在所述金属层上的多晶硅层; 以及与所述多晶硅层相邻形成并与所述金属层隔开形成的源极区域和漏极区域。 还提供了一种形成半导体器件的方法，包括形成衬底和源极和漏极层; 形成凹部并在其中沉积栅极绝缘层; 在所述栅绝缘层上形成第一导电层; 通过使所述第一导电层凹陷来形成第一导电层图案; 在所述第一导电层图案上形成第二导电层; 通过图案化所述第二导电层以与所述源极和漏极层重叠而形成第二导电层图案; 在第二导电层图案和源极和漏极层上沉积绝缘层; 并且平坦化绝缘层以在第二导电层图案上形成帽。

    RECESS GATE TRANSISTOR
    8.
    发明申请
    RECESS GATE TRANSISTOR 审中-公开
    记忆闸门晶体管

    公开(公告)号：US20120009976A1

    公开(公告)日：2012-01-12

    申请号：US13242724

    申请日：2011-09-23

    申请人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    发明人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    IPC分类号： H04M1/00 ,  G11C11/34 ,  H01L27/088

    CPC分类号： H01L29/4236 ,  H01L29/66621

    摘要： A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

    摘要翻译： 提供一种形成半导体器件的方法，包括：通过图案化绝缘层在衬底上形成多个硬掩模; 在衬底中形成多个沟槽，每个沟槽具有设置在两个相邻掩模之间并且从底部到上部垂直延伸的沟槽壁; 在硬掩模和沟槽壁上形成绝缘层; 在绝缘层上形成导电层; 蚀刻导电层以形成导电层图案以填充沟槽的底部; 在导电层图案和沟槽壁上沉积缓冲层; 以及用覆盖层填充沟槽的上部。

    RECESS GATE TRANSISTOR
    9.
    发明申请
    RECESS GATE TRANSISTOR 有权
    记忆闸门晶体管

    公开(公告)号：US20090261420A1

    公开(公告)日：2009-10-22

    申请号：US12332877

    申请日：2008-12-11

    申请人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    发明人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    IPC分类号： H01L25/00 ,  H01L21/4763 ,  H01L29/78

    CPC分类号： H01L29/4236 ,  H01L29/66621

    摘要： A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

    摘要翻译： 提供一种形成半导体器件的方法，包括：通过图案化绝缘层在衬底上形成多个硬掩模; 在衬底中形成多个沟槽，每个沟槽具有设置在两个相邻掩模之间并且从底部到上部垂直延伸的沟槽壁; 在硬掩模和沟槽壁上形成绝缘层; 在绝缘层上形成导电层; 蚀刻导电层以形成导电层图案以填充沟槽的底部; 在导电层图案和沟槽壁上沉积缓冲层; 以及用覆盖层填充沟槽的上部。

    RECESS GATE TRANSISTOR
    10.
    发明申请
    RECESS GATE TRANSISTOR 有权
    记忆闸门晶体管

    公开(公告)号：US20090173994A1

    公开(公告)日：2009-07-09

    申请号：US12251054

    申请日：2008-10-14

    申请人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

    发明人： Ji-Young Min ,  Si-Hyung Lee ,  Heedon Hwang ,  Si-Young Choi ,  Sangbom Kang ,  Dongsoo Woo

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66553 ,  H01L21/28079 ,  H01L21/28114 ,  H01L29/4236

    摘要： A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

    摘要翻译： 提供半导体器件的凹槽，其包括：形成有凹部的基板; 形成在所述凹部的底部的金属层; 形成在所述金属层上的多晶硅层; 以及与所述多晶硅层相邻形成并与所述金属层隔开形成的源极区域和漏极区域。 还提供了一种形成半导体器件的方法，包括形成衬底和源极和漏极层; 形成凹部并在其中沉积栅极绝缘层; 在所述栅绝缘层上形成第一导电层; 通过使所述第一导电层凹陷来形成第一导电层图案; 在所述第一导电层图案上形成第二导电层; 通过图案化所述第二导电层以与所述源极和漏极层重叠而形成第二导电层图案; 在第二导电层图案和源极和漏极层上沉积绝缘层; 并且平坦化绝缘层以在第二导电层图案上形成帽。