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15 条记录 (耗时 0.026 秒)

    METHODS OF FORMING ELECTRONIC DEVICES INCLUDING ELECTRODES WITH INSULATING SPACERS THEREON
    3.
    发明申请
    METHODS OF FORMING ELECTRONIC DEVICES INCLUDING ELECTRODES WITH INSULATING SPACERS THEREON 失效
    形成包含绝缘间隔电极的电子器件的方法

    公开(公告)号：US20080096347A1

    公开(公告)日：2008-04-24

    申请号：US11956360

    申请日：2007-12-14

    申请人： In-joon Yeo ,  Tae-hyuk Ahn ,  Kwang-wook Lee ,  Jung-woo Seo ,  Jeong-sic Jeon

    发明人： In-joon Yeo ,  Tae-hyuk Ahn ,  Kwang-wook Lee ,  Jung-woo Seo ,  Jeong-sic Jeon

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/90 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

    摘要： An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.

    摘要翻译： 电子器件可以包括衬底，衬底上的导电层和绝缘间隔物。 导电电极可以具有远离衬底延伸的电极壁。 绝缘间隔物可以设置在电极壁上，电极壁的部分在衬底和绝缘间隔物之间​​没有绝缘间隔物，并且电极最远离衬底的部分可以没有绝缘间隔物。 还讨论了相关的方法和结构。

    Electronic devices including electrode walls with insulating layers thereon
    5.
    发明授权
    Electronic devices including electrode walls with insulating layers thereon 失效
    电子设备包括其上具有绝缘层的电极壁

    公开(公告)号：US07888725B2

    公开(公告)日：2011-02-15

    申请号：US12245218

    申请日：2008-10-03

    申请人： In-joon Yeo ,  Tae-hyuk Ahn ,  Kwang-wook Lee ,  Jung-woo Seo ,  Jeong-sic Jeon

    发明人： In-joon Yeo ,  Tae-hyuk Ahn ,  Kwang-wook Lee ,  Jung-woo Seo ,  Jeong-sic Jeon

    IPC分类号： H01L29/94

    CPC分类号： H01L28/90 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

    摘要： An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer.

    摘要翻译： 电子器件可以包括衬底和在衬底上的多个导电电极。 每个导电电极可以具有远离基板延伸的相应电极壁，并且至少一个导电电极的电极壁可以包括凹部。 此外，可以在电极壁上设置绝缘层，并且电极壁的部分在基板和绝缘层之间可以没有绝缘层。

    Semiconductor memory device having local etch stopper and method of manufacturing the same
    9.
    发明授权
    Semiconductor memory device having local etch stopper and method of manufacturing the same 有权
    具有局部蚀刻停止器的半导体存储器件及其制造方法

    公开(公告)号：US07851354B2

    公开(公告)日：2010-12-14

    申请号：US12267785

    申请日：2008-11-10

    申请人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

    发明人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76895 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

    摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

    摘要翻译： 半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。 该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。 形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。 在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

    Method of manufacturing a semiconductor memory device
    10.
    发明申请
    Method of manufacturing a semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US20050079673A1

    公开(公告)日：2005-04-14

    申请号：US10954835

    申请日：2004-09-29

    申请人： Jung-woo Seo ,  Tae-hyuk Ahn ,  Jeong-sic Jeon

    发明人： Jung-woo Seo ,  Tae-hyuk Ahn ,  Jeong-sic Jeon

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76895 ,  H01L21/76802 ,  H01L21/76831 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

    摘要： Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

    摘要翻译： 通过首先形成覆盖导电垫的第一绝缘层来制造半导体存储器。 接下来形成和图案位线导电层和第二绝缘层以暴露第一绝缘层的一部分。 形成覆盖第一绝缘层的暴露表面的第三绝缘层。 露出位线导电层图案的上表面和第三绝缘层的上表面。 去除第三绝缘层和第一绝缘层的一部分以暴露导电焊盘。 在位线导电层图案和第一绝缘层的侧壁上形成间隔物。 分别在位线导电层图案和第一间隔物的侧壁上形成绝缘层图案和第二间隔层，并且形成与导电焊盘接触的导电插塞。