公开(公告)号：US09576944B2

公开(公告)日：2017-02-21

申请号：US14959276

申请日：2015-12-04

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Christian Jaeger ,  Joachim Mahler ,  Daniel Pedone ,  Anton Prueckl ,  Hans-Joachim Schulze ,  Andre Schwagmann ,  Patrick Schwarz

IPC: H01L29/94 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01C7/04 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813 ,  H01L45/00

Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

Abstract translation: 半导体器件包括电耦合到晶体管单元的源极区的第一负载端子。 栅极端子电耦合到电容耦合到晶体管单元的体区的栅电极。 源区和体区形成在半导体部分中。 热电阻元件热连接到半导体部分，并且电连接在栅极端子和第一负载端子之间。 在对于半导体器件规定的最大工作温度之上，耐温元件的电阻在至多50开尔文的临界温度范围内降低至少两个数量级。

公开(公告)号：US20160163689A1

公开(公告)日：2016-06-09

申请号：US14959276

申请日：2015-12-04

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Christian Jaeger ,  Joachim Mahler ,  Daniel Pedone ,  Anton Prueckl ,  Hans-Joachim Schulze ,  Andre Schwagmann ,  Patrick Schwarz

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01C7/04 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813 ,  H01L45/00

Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

Abstract translation: 半导体器件包括电耦合到晶体管单元的源极区的第一负载端子。 栅极端子电耦合到电容耦合到晶体管单元的体区的栅电极。 源区和体区形成在半导体部分中。 热电阻元件热连接到半导体部分，并且电连接在栅极端子和第一负载端子之间。 在对于半导体器件规定的最大工作温度之上，耐温元件的电阻在至多50开尔文的临界温度范围内降低至少两个数量级。

公开(公告)号：US09905634B2

公开(公告)日：2018-02-27

申请号：US15188695

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Andre Schwagmann ,  Elmar Falck ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/225 ,  H01L21/263 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/0619 ,  H01L21/2253 ,  H01L21/263 ,  H01L21/26506 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66325 ,  H01L29/66674 ,  H01L29/7391 ,  H01L29/7393 ,  H01L29/7801

Abstract: A semiconductor device having a first load terminal, a second load terminal and a semiconductor body is presented. The semiconductor body comprises an active region configured to conduct a load current between the first load terminal and the second load terminal and a junction termination region surrounding the active region. The semiconductor body includes a drift layer arranged within both the active region and the junction termination region and having dopants of a first conductivity type at a drift layer dopant concentration of equal to or less than 1014 cm−3; a body zone arranged in the active region and having dopants of a second conductivity type complementary to the first conductivity type and isolating the drift layer from the first load terminal; a guard zone arranged in the junction termination region and having dopants of the second conductivity type and being configured to extend a depletion region formed by a transition between the drift layer and the body zone; a field stop zone arranged adjacent to the guard zone, the field stop zone having dopants of the first conductivity type at a field stop zone dopant concentration that is higher than the drift layer dopant concentration by a factor of at least 2; a low doped zone arranged adjacent to the field stop zone, the low doped zone having dopants of the first conductivity type at a dopant concentration that is lower than the drift layer dopant concentration by a factor of at least 1.5, wherein the body zone, the guard zone, the field stop zone and the low doped zone are arranged in the semiconductor body such that they exhibit a common depth range (DR) of at least 1 μm along a vertical extension direction (Z).

公开(公告)号：US20170005163A1

公开(公告)日：2017-01-05

申请号：US15188695

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Andre Schwagmann ,  Elmar Falck ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/225 ,  H01L29/10

CPC classification number: H01L29/0619 ,  H01L21/2253 ,  H01L21/263 ,  H01L21/26506 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66325 ,  H01L29/66674 ,  H01L29/7391 ,  H01L29/7393 ,  H01L29/7801

Abstract: A semiconductor device having a first load terminal, a second load terminal and a semiconductor body is presented. The semiconductor body comprises an active region configured to conduct a load current between the first load terminal and the second load terminal and a junction termination region surrounding the active region. The semiconductor body includes a drift layer arranged within both the active region and the junction termination region and having dopants of a first conductivity type at a drift layer dopant concentration of equal to or less than 1014 cm−3; a body zone arranged in the active region and having dopants of a second conductivity type complementary to the first conductivity type and isolating the drift layer from the first load terminal; a guard zone arranged in the junction termination region and having dopants of the second conductivity type and being configured to extend a depletion region formed by a transition between the drift layer and the body zone; a field stop zone arranged adjacent to the guard zone, the field stop zone having dopants of the first conductivity type at a field stop zone dopant concentration that is higher than the drift layer dopant concentration by a factor of at least 2; a low doped zone arranged adjacent to the field stop zone, the low doped zone having dopants of the first conductivity type at a dopant concentration that is lower than the drift layer dopant concentration by a factor of at least 1.5, wherein the body zone, the guard zone, the field stop zone and the low doped zone are arranged in the semiconductor body such that they exhibit a common depth range (DR) of at least 1 μm along a vertical extension direction (Z).

Abstract translation: 提出了具有第一负载端子，第二负载端子和半导体本体的半导体器件。 半导体本体包括有源区域，被配置为在第一负载端子和第二负载端子之间传导负载电流，以及围绕有源区域的接合端接区域。 半导体本体包括布置在有源区和结端接区内的漂移层，并具有等于或小于1014cm-3的漂移层掺杂剂浓度的第一导电类型的掺杂剂; 身体区域，布置在有源区域中并具有与第一导电类型互补的第二导电类型的掺杂剂，并将漂移层与第一负载端子隔离; 保护区，布置在所述连接终端区域中并且具有所述第二导电类型的掺杂剂并且被配置为延伸由所述漂移层和所述体区之间的过渡形成的耗尽区; 与所述保护区相邻设置的场停止区，所述场停止区具有比所述漂移层掺杂剂浓度高至少2的场阻带掺杂剂浓度的所述第一导电类型的掺杂剂; 低掺杂区，其布置成与所述场停止区相邻，所述低掺杂区具有掺杂浓度低于所述漂移层掺杂剂浓度至少为1.5的掺杂浓度的第一导电类型，其中所述体区， 保护区域，场阻挡区域和低掺杂区域布置在半导体本体中，使得它们沿垂直延伸方向（Z）呈现至少1μm的公共深度范围（DR）。