公开(公告)号：US12033972B2

公开(公告)日：2024-07-09

申请号：US17090941

申请日：2020-11-06

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L24/48 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02288 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/83 ,  H01L24/85 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0346 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45611 ,  H01L2224/45618 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45649 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/45664 ,  H01L2224/45666 ,  H01L2224/4567 ,  H01L2224/45671 ,  H01L2224/45672 ,  H01L2224/4568 ,  H01L2224/45686 ,  H01L2224/4569 ,  H01L2224/45693 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48507 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/85801 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/45144 ,  H01L2924/00015 ,  H01L2224/45139 ,  H01L2924/00015 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/45572 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/45644 ,  H01L2224/45147 ,  H01L2924/01046 ,  H01L2224/45639 ,  H01L2924/00014 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45669 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2224/45565 ,  H01L2224/45139 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45611 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45618 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45649 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45655 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45657 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45666 ,  H01L2224/45655 ,  H01L2924/01029 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45639 ,  H01L2224/45664 ,  H01L2924/01028 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05681 ,  H01L2924/00014 ,  H01L2224/05657 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/01056 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/43848

Abstract: A method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

公开(公告)号：US11682644B2

公开(公告)日：2023-06-20

申请号：US17361950

申请日：2021-06-29

Applicant: Infineon Technologies AG

Inventor： Swee Kah Lee ,  Sook Woon Chan ,  Fong Mei Lum ,  Joachim Mahler ,  Muhammad Muhammat Sanusi

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/11822 ,  H01L2224/1357 ,  H01L2224/1362 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/13638 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/81801

Abstract: A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

公开(公告)号：US10854547B2

公开(公告)日：2020-12-01

申请号：US16279370

申请日：2019-02-19

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Georg Meyer-Berg ,  Guenter Tutsch

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L25/07 ,  H01L23/00

Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.

公开(公告)号：US10396007B2

公开(公告)日：2019-08-27

申请号：US15448018

申请日：2017-03-02

Applicant: Infineon Technologies AG

Inventor： Sook Woon Chan ,  Chau Fatt Chiang ,  Kok Yau Chua ,  Soon Lock Goh ,  Swee Kah Lee ,  Joachim Mahler ,  Mei Chin Ng ,  Beng Keh See ,  Guan Choon Matthew Nelson Tee

IPC: H01L23/552 ,  H01L23/31 ,  C09D5/00 ,  C09D201/00 ,  C23C18/16 ,  C23C18/18 ,  C23C18/34 ,  H01L21/56 ,  H01L23/29 ,  H01L23/66 ,  H01L23/00 ,  C09D5/24

Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.

公开(公告)号：US20190109112A1

公开(公告)日：2019-04-11

申请号：US15725796

申请日：2017-10-05

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  C09J5/06

Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.

公开(公告)号：US20180338379A1

公开(公告)日：2018-11-22

申请号：US15982778

申请日：2018-05-17

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Joachim Mahler

IPC: H05K3/32 ,  B22F7/06 ,  H05K7/02

Abstract: An electronic device includes a component, an electronic component, and a joining material arranged between a surface of the component and a surface of the electronic component. Spacer elements are embedded in the joining material. Interconnects are arranged between the spacer elements and the surface of the component, and between the spacer elements and the surface of the electronic component.

公开(公告)号：US10038105B2

公开(公告)日：2018-07-31

申请号：US15229828

申请日：2016-08-05

Applicant: Infineon Technologies AG

Inventor： Thomas Basler ,  Joachim Mahler ,  Hans-Joachim Schulze

IPC: H01L29/861 ,  H01L29/08 ,  H01L29/36 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/861 ,  H01L29/0619 ,  H01L29/08 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7393 ,  H01L29/872

Abstract: A semiconductor device includes at least one highly doped region of an electrical device arrangement formed in a semiconductor substrate and a contact structure including an NTC (negative temperature coefficient of resistance) portion arranged adjacent to the at least one highly doped region at a front side surface of the semiconductor substrate. The NTC portion includes a negative temperature coefficient of resistance material.

公开(公告)号：US10020245B2

公开(公告)日：2018-07-10

申请号：US14150795

申请日：2014-01-09

Applicant: Infineon Technologies AG

Inventor： Henrik Ewe ,  Joachim Mahler ,  Anton Prueckl ,  Stefan Landau

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H05K1/18 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H05K1/05 ,  H05K3/46

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/05 ,  H05K1/185 ,  H05K1/188 ,  H05K3/4644 ,  H05K2201/09745 ,  H05K2201/09972 ,  H05K2203/0353 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.

公开(公告)号：US09984897B2

公开(公告)日：2018-05-29

申请号：US15268674

申请日：2016-09-19

Applicant: Infineon Technologies AG

Inventor： Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini ,  Franz-Peter Kalz

IPC: H01L21/48 ,  H01L23/373 ,  H01L21/77 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L21/4807 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/77 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49586 ,  H01L24/27 ,  H01L24/743 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.

公开(公告)号：US09852918B2

公开(公告)日：2017-12-26

申请号：US14835750

申请日：2015-08-26

Applicant: Infineon Technologies AG

Inventor： Peh Hean Teh ,  Jagen Krishnan ,  Swee Kah Lee ,  Poh Cheng Lim ,  Joachim Mahler ,  Chew Theng Tai ,  Yik Yee Tan ,  Soon Lock Goh

IPC: H01L23/29 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  C09J163/00

CPC classification number: H01L21/3105 ,  C09J163/00 ,  H01L21/56 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49555 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/8392 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and a plurality of capsules in the encapsulant, wherein the capsules comprise a core comprising an additive and comprise a shell, in particular a crackable shell, enclosing the core.