公开(公告)号：US10020245B2

公开(公告)日：2018-07-10

申请号：US14150795

申请日：2014-01-09

Applicant: Infineon Technologies AG

Inventor： Henrik Ewe ,  Joachim Mahler ,  Anton Prueckl ,  Stefan Landau

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H05K1/18 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H05K1/05 ,  H05K3/46

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/05 ,  H05K1/185 ,  H05K1/188 ,  H05K3/4644 ,  H05K2201/09745 ,  H05K2201/09972 ,  H05K2203/0353 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.

公开(公告)号：US09607966B2

公开(公告)日：2017-03-28

申请号：US14676877

申请日：2015-04-02

Applicant: Infineon Technologies AG

Inventor： Anton Prueckl

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L25/0655 ,  H01L23/3157 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/95 ,  H01L25/16 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.

公开(公告)号：US09018773B2

公开(公告)日：2015-04-28

申请号：US14144596

申请日：2013-12-31

Applicant: Infineon Technologies AG

Inventor： Anton Prueckl

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L23/495 ,  H01L25/16

CPC classification number: H01L25/0655 ,  H01L23/3157 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/95 ,  H01L25/16 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.

Abstract translation: 提供了芯片布置。 芯片布置包括：电连接到第一芯片载体顶侧的第一芯片; 电连接到第二芯片载体顶侧的第二芯片; 以及电绝缘材料，其被配置为至少部分地围绕所述第一芯片载体和所述第二芯片载体; 至少一个电互连配置成通过电绝缘材料将第一芯片电接触到第二芯片; 一个或多个第一导电部分形成在第一芯片载体顶侧和第二芯片载体顶侧中的至少一个上并与其电接触，以及一个或多个第二导电部分，形成在第一和第二导电部分之间， 芯片载体底侧和第二芯片载体底侧。

公开(公告)号：US20140110864A1

公开(公告)日：2014-04-24

申请号：US14144596

申请日：2013-12-31

Applicant: Infineon Technologies AG

Inventor： Anton Prueckl

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/3157 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/95 ,  H01L25/16 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.

Abstract translation: 提供了芯片布置。 芯片布置包括：电连接到第一芯片载体顶侧的第一芯片; 电连接到第二芯片载体顶侧的第二芯片; 以及电绝缘材料，其被配置为至少部分地围绕所述第一芯片载体和所述第二芯片载体; 至少一个电互连配置成通过电绝缘材料将第一芯片电接触到第二芯片; 一个或多个第一导电部分形成在第一芯片载体顶侧和第二芯片载体顶侧中的至少一个上并与其电接触，以及一个或多个第二导电部分，形成在第一和第二导电部分中的至少一个上， 芯片载体底侧和第二芯片载体底侧。

公开(公告)号：US09576944B2

公开(公告)日：2017-02-21

申请号：US14959276

申请日：2015-12-04

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Christian Jaeger ,  Joachim Mahler ,  Daniel Pedone ,  Anton Prueckl ,  Hans-Joachim Schulze ,  Andre Schwagmann ,  Patrick Schwarz

IPC: H01L29/94 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01C7/04 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813 ,  H01L45/00

Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

Abstract translation: 半导体器件包括电耦合到晶体管单元的源极区的第一负载端子。 栅极端子电耦合到电容耦合到晶体管单元的体区的栅电极。 源区和体区形成在半导体部分中。 热电阻元件热连接到半导体部分，并且电连接在栅极端子和第一负载端子之间。 在对于半导体器件规定的最大工作温度之上，耐温元件的电阻在至多50开尔文的临界温度范围内降低至少两个数量级。

公开(公告)号：US09443760B2

公开(公告)日：2016-09-13

申请号：US14543557

申请日：2014-11-17

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/13 ,  H01L23/433 ,  H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L25/07 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/224 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/24175 ,  H01L2224/244 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/35 ,  H01L2224/352 ,  H01L2224/3701 ,  H01L2224/37113 ,  H01L2224/37118 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/40095 ,  H01L2224/40155 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41171 ,  H01L2224/48155 ,  H01L2224/48175 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82104 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84447 ,  H01L2224/92244 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/07811 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01023 ,  H01L2224/45099

Abstract: An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.

Abstract translation: 电子设备包括与第一芯片载体隔离的第一芯片载体和第二芯片载体。 第一功率半导体芯片安装在电连接到第一芯片载体上。 第二功率半导体芯片安装在第二芯片载体上并电连接到第二芯片载体。 电绝缘材料被配置为至少部分地围绕第一功率半导体芯片和第二功率半导体芯片。 电互连被配置为将第一功率半导体芯片电连接到第二功率半导体芯片，其中电互连具有接触夹和电沉积导体中的至少一个。

公开(公告)号：US20140117565A1

公开(公告)日：2014-05-01

申请号：US14150795

申请日：2014-01-09

Applicant: Infineon Technologies AG

Inventor： Henrik Ewe ,  Joachim Mahler ,  Anton Prueckl ,  Stefan Landau

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/05 ,  H05K1/185 ,  H05K1/188 ,  H05K3/4644 ,  H05K2201/09745 ,  H05K2201/09972 ,  H05K2203/0353 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.

Abstract translation: 公开了一种制造层压电子装置的方法。 一个实施例提供载体，载体限定第一主表面和与第一主表面相对的第二主表面。 载体具有形成在第一主表面中的凹陷图案。 第一半导体芯片附接在第一和第二主表面之一上。 覆盖在其上附着有第一半导体芯片的载体的主表面上的第一绝缘层和形成第一半导体芯片。 然后沿着凹槽图案将载体分离成多个部分。

公开(公告)号：US20160163689A1

公开(公告)日：2016-06-09

申请号：US14959276

申请日：2015-12-04

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Christian Jaeger ,  Joachim Mahler ,  Daniel Pedone ,  Anton Prueckl ,  Hans-Joachim Schulze ,  Andre Schwagmann ,  Patrick Schwarz

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01C7/04 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813 ,  H01L45/00

Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

Abstract translation: 半导体器件包括电耦合到晶体管单元的源极区的第一负载端子。 栅极端子电耦合到电容耦合到晶体管单元的体区的栅电极。 源区和体区形成在半导体部分中。 热电阻元件热连接到半导体部分，并且电连接在栅极端子和第一负载端子之间。 在对于半导体器件规定的最大工作温度之上，耐温元件的电阻在至多50开尔文的临界温度范围内降低至少两个数量级。

公开(公告)号：US20150064844A1

公开(公告)日：2015-03-05

申请号：US14543557

申请日：2014-11-17

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

IPC: H01L21/768 ,  H01L25/00

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/224 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/24175 ,  H01L2224/244 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/35 ,  H01L2224/352 ,  H01L2224/3701 ,  H01L2224/37113 ,  H01L2224/37118 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/40095 ,  H01L2224/40155 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41171 ,  H01L2224/48155 ,  H01L2224/48175 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82104 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84447 ,  H01L2224/92244 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/07811 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01023 ,  H01L2224/45099

Abstract: An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.

Abstract translation: 电子设备包括与第一芯片载体隔离的第一芯片载体和第二芯片载体。 第一功率半导体芯片安装在电连接到第一芯片载体上。 第二功率半导体芯片安装在第二芯片载体上并电连接到第二芯片载体。 电绝缘材料被配置为至少部分地围绕第一功率半导体芯片和第二功率半导体芯片。 电互连被配置为将第一功率半导体芯片电连接到第二功率半导体芯片，其中电互连具有接触夹和电沉积导体中的至少一个。