公开(公告)号：US10396018B2

公开(公告)日：2019-08-27

申请号：US15822745

申请日：2017-11-27

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Chan Lam Cha ,  Wei Han Koo ,  Andreas Kucher ,  Theng Chao Long

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/495 ,  H03K17/687 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H02M1/088 ,  H02P27/04

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

公开(公告)号：US20190164873A1

公开(公告)日：2019-05-30

申请号：US15822745

申请日：2017-11-27

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Chan Lam Cha ,  Wei Han Koo ,  Andreas Kucher ,  Theng Chao Long

IPC: H01L23/495 ,  H03K17/687 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49575 ,  H01L21/4803 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H02M1/088 ,  H02P27/04 ,  H03K17/6871

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

公开(公告)号：US11444011B2

公开(公告)日：2022-09-13

申请号：US17095947

申请日：2020-11-12

Applicant: Infineon Technologies AG

Inventor： Woon Yik Yong ,  Andreas Kucher ,  Chia-Yen Lee ,  Shao Ping Wan

IPC: H01L23/495 ,  H01L23/00

Abstract: An embodiment of a semiconductor package includes a leadframe having leads, a mold compound partly encasing the leadframe so that the leads protrude from the mold compound, a power transistor die attached to the leadframe at a first side of the leadframe, and a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement. The driver die is configured to control the power transistor die. The driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe. Corresponding methods of manufacturing the semiconductor package are also described.

公开(公告)号：US20210066172A1

公开(公告)日：2021-03-04

申请号：US17095947

申请日：2020-11-12

Applicant: Infineon Technologies AG

Inventor： Woon Yik Yong ,  Andreas Kucher ,  Chia-Yen Lee ,  Shao Ping Wan

IPC: H01L23/495 ,  H01L23/00

Abstract: An embodiment of a semiconductor package includes a leadframe having leads, a mold compound partly encasing the leadframe so that the leads protrude from the mold compound, a power transistor die attached to the leadframe at a first side of the leadframe, and a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement. The driver die is configured to control the power transistor die. The driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe. Corresponding methods of manufacturing the semiconductor package are also described.