公开(公告)号：US20150203350A1

公开(公告)日：2015-07-23

申请号：US14675672

申请日：2015-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Thoralf KAUTZSCH ,  Boris BINDER ,  Torsten HELM ,  Stefan KOLB ,  Marc PROBST ,  Uwe RUDOLPH

IPC: B81C1/00

CPC classification number: B81C1/00523 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C1/0038

Abstract: Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.

Abstract translation: 描述和描述了与半导体制造相关的实施例和具有半导体结构的半导体器件。

公开(公告)号：US20230123410A1

公开(公告)日：2023-04-20

申请号：US18046289

申请日：2022-10-13

Applicant: Infineon Technologies AG

Inventor： Stefano PARASCANDOLA ,  Dirk OFFENBERG ,  Boris BINDER

IPC: H01L27/146 ,  H01L31/102 ,  H01L31/18

Abstract: A heteroepitaxial semiconductor device includes a bulk semiconductor substrate, a seed layer including a first semiconductor material, the seed layer being arranged at a first side of the bulk semiconductor substrate and including a first side facing the bulk semiconductor substrate, an opposing second side and lateral sides connecting the first and second sides, a separation layer arranged between the bulk semiconductor substrate and the seed layer, a heteroepitaxial structure grown on the second side of the seed layer and including a second semiconductor material, different from the first semiconductor material, and a dielectric material layer arranged on the seed layer and at least partially encapsulating the heteroepitaxial structure, wherein the dielectric material layer also covers the lateral sides of the seed layer.

公开(公告)号：US20210013087A1

公开(公告)日：2021-01-14

申请号：US16922711

申请日：2020-07-07

Applicant: Infineon Technologies AG

Inventor： Andre ROETH ,  Boris BINDER ,  Thoralf KAUTZSCH ,  Uwe RUDOLPH ,  Maik STEGEMANN ,  Mirko VOGT

IPC: H01L21/764 ,  H01L21/3065

Abstract: In a method for producing a buried cavity in a semiconductor substrate, trenches are produced in a surface of a semiconductor substrate down to a depth that is greater than cross-sectional dimensions of the respective trench in a cross section perpendicular to the depth, wherein a protective layer is formed on sidewalls of the trenches. Isotropic etching through bottom regions of the trenches is carried out. After carrying out the isotropic etching, the enlarged trenches are closed by applying a semiconductor epitaxial layer to the surface of the semiconductor substrate.