公开(公告)号：US11562789B2

公开(公告)日：2023-01-24

申请号：US17117713

申请日：2020-12-10

Applicant: Infineon Technologies AG

Inventor： David Mueller ,  Wolf Allers ,  Christian Peters

IPC: G11C17/16 ,  G11C17/18 ,  G11C13/00 ,  G11C7/10

Abstract: In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.

公开(公告)号：US20150255136A1

公开(公告)日：2015-09-10

申请号：US14714796

申请日：2015-05-18

Applicant: Infineon Technologies AG

Inventor： David Mueller ,  Wolf Allers ,  Mihail Jefremow

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/02 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1659 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.

Abstract translation: 本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。 在一个示例中，用于读取存储器单元的系统包括感测路径和反向路径。 通过感测路径提供参考电流，并且通过感测路径中的第一采样元件进行采样，并且通过反向感测路径提供来自存储器单元的单元电流，并且经由反向感测路径中的第二采样元件进行采样 。 随后，存储器单元与反向感测路径断开，通过感测路径提供单元电流，参考源与感测路径断开，并通过反向感测路径提供参考电流。 然后，输出电平由电池和参考电流根据采样的参考和采样单元电流工作来确定。

公开(公告)号：US09524766B2

公开(公告)日：2016-12-20

申请号：US14714796

申请日：2015-05-18

Applicant: Infineon Technologies AG

Inventor： David Mueller ,  Wolf Allers ,  Mihail Jefremow

IPC: G11C11/00 ,  G11C11/16 ,  G11C7/02 ,  G11C7/12 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C11/1673 ,  G11C7/02 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1659 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.

公开(公告)号：US20140133250A1

公开(公告)日：2014-05-15

申请号：US14160784

申请日：2014-01-22

Applicant: Infineon Technologies AG

Inventor： David Mueller ,  Thomas Nirschl

IPC: G11C7/06 ,  G11C7/08

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18

Abstract: Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.

Abstract translation: 本公开的一些实施例涉及促进快速和准确的读取操作的读出放大器架构。 感测放大器架构包括用于其第一读出放大器级的折叠共源共栅放大器和用于为感测放大器的感测线和参考感测线建立预充电状态的预充电电路。 预充电电路和折叠共源共栅放大器各自包括相同尺寸的一个或多个共源共栅晶体管，并且在其栅极上接收相同的偏置电压。 该架构在相对较小的占地面积中提供快速准确的读取操作，从而提供了成本和性能的良好组合。

公开(公告)号：US09240225B2

公开(公告)日：2016-01-19

申请号：US14160784

申请日：2014-01-22

Applicant: Infineon Technologies AG

Inventor： David Mueller ,  Thomas Nirschl

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18

Abstract: Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.

Abstract translation: 本公开的一些实施例涉及促进快速和准确的读取操作的读出放大器架构。 感测放大器架构包括用于其第一读出放大器级的折叠共源共栅放大器和用于为感测放大器的感测线和参考感测线建立预充电状态的预充电电路。 预充电电路和折叠共源共栅放大器各自包括相同尺寸的一个或多个共源共栅晶体管，并且在其栅极上接收相同的偏置电压。 该架构在相对较小的占地面积中提供快速准确的读取操作，从而提供了成本和性能的良好组合。