公开(公告)号：US20180342447A1

公开(公告)日：2018-11-29

申请号：US15985313

申请日：2018-05-21

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Gilles Delarozee ,  Daniel Schleisser ,  Christopher Spielman ,  Thomas Stoek

IPC: H01L23/495 ,  H02M7/5387 ,  H02M1/084 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49575 ,  B60Y2200/91 ,  H01L21/4825 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2924/181 ,  H02M1/084 ,  H02M7/003 ,  H02M7/53871 ,  H01L2924/00012

Abstract: A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.

公开(公告)号：US10727151B2

公开(公告)日：2020-07-28

申请号：US15605091

申请日：2017-05-25

Applicant: Infineon Technologies AG

Inventor： Liu Chen ,  Teck Sim Lee ,  Jia Yi Wong ,  Wei Han Koo ,  Thomas Stoeck ,  Gilles Delarozee

IPC: H01L23/367 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56 ,  H01L23/433 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/373

Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.

公开(公告)号：US20180342438A1

公开(公告)日：2018-11-29

申请号：US15605091

申请日：2017-05-25

Applicant: Infineon Technologies AG

Inventor： Liu Chen ,  Teck Sim Lee ,  Jia Yi Wong ,  Wei Han Koo ,  Thomas Stoek ,  Gilles Delarozee

IPC: H01L23/367 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56

Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.

公开(公告)号：US10319671B2

公开(公告)日：2019-06-11

申请号：US15985313

申请日：2018-05-21

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Gilles Delarozee ,  Daniel Schleisser ,  Christopher Spielman ,  Thomas Stoek

IPC: H02M7/00 ,  H01L21/48 ,  H01L23/31 ,  H02M1/084 ,  H01L23/495 ,  H02M7/5387

Abstract: A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.

公开(公告)号：US09978672B1

公开(公告)日：2018-05-22

申请号：US15603476

申请日：2017-05-24

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Gilles Delarozee ,  Daniel Schleisser ,  Christopher Spielman ,  Thomas Stoek

IPC: H01L23/495 ,  H01L21/00 ,  H01L23/52 ,  H02M7/5387 ,  H02M1/084 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49575 ,  B60Y2200/91 ,  H01L21/4825 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49562 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2924/181 ,  H02M7/003 ,  H01L2924/00012

Abstract: A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.