公开(公告)号：US20130224942A1

公开(公告)日：2013-08-29

申请号：US13854258

申请日：2013-04-01

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在工件的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在工件的第一区域中形成第一晶体管，其包括CMOS器件的NMOS FET，而在工件的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US09087919B2

公开(公告)日：2015-07-21

申请号：US14251193

申请日：2014-04-11

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的衬底上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在衬底的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在衬底的第一区域中形成第一晶体管，该第一晶体管包括CMOS器件的NMOS FET，而衬底的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US20150364328A1

公开(公告)日：2015-12-17

申请号：US14744781

申请日：2015-06-19

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的衬底上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在衬底的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在衬底的第一区域中形成第一晶体管，该第一晶体管包括CMOS器件的NMOS FET，而衬底的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US20140220770A1

公开(公告)日：2014-08-07

申请号：US14251193

申请日：2014-04-11

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/8238 ,  H01L29/40

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的衬底上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在衬底的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在衬底的第一区域中形成第一晶体管，该第一晶体管包括CMOS器件的NMOS FET，而衬底的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US08778765B2

公开(公告)日：2014-07-15

申请号：US13854258

申请日：2013-04-01

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/00

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在工件的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在工件的第一区域中形成第一晶体管，其包括CMOS器件的NMOS FET，而在工件的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US09917191B2

公开(公告)日：2018-03-13

申请号：US14935067

申请日：2015-11-06

Applicant: Infineon Technologies AG

Inventor： Manfred Eller ,  Jin-Ping Han

IPC: H01L33/00 ,  H01L21/332 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

公开(公告)号：US09659778B2

公开(公告)日：2017-05-23

申请号：US14744781

申请日：2015-06-19

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

公开(公告)号：US20160064564A1

公开(公告)日：2016-03-03

申请号：US14935067

申请日：2015-11-06

Applicant: Infineon Technologies AG

Inventor： Manfred Eller ,  Jin-Ping Han

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.