公开(公告)号：US20170344690A1

公开(公告)日：2017-11-30

申请号：US15681934

申请日：2017-08-21

Applicant: Infineon Technologies AG

Inventor： Henning Haffner ,  Manfred Eller ,  Richard Lindsay

IPC: G06F17/50 ,  G03F1/00 ,  H01L21/033 ,  H01L21/28 ,  H01L27/085 ,  H01L27/082 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F2217/12 ,  H01L21/0334 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/082 ,  H01L27/085 ,  H01L27/088 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T29/41

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

公开(公告)号：US09767244B2

公开(公告)日：2017-09-19

申请号：US15093646

申请日：2016-04-07

Applicant: Infineon Technologies AG

Inventor： Henning Haffner ,  Manfred Eller ,  Richard Lindsay

IPC: G06F17/50 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/02 ,  G03F1/00 ,  H01L27/082 ,  H01L27/085 ,  H01L21/033 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F2217/12 ,  H01L21/0334 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/082 ,  H01L27/085 ,  H01L27/088 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T29/41

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

公开(公告)号：US10089430B2

公开(公告)日：2018-10-02

申请号：US15681934

申请日：2017-08-21

Applicant: Infineon Technologies AG

Inventor： Henning Haffner ,  Manfred Eller ,  Richard Lindsay

IPC: G06F17/50 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/02 ,  G03F1/00 ,  H01L27/082 ,  H01L27/085 ,  H01L21/033 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

公开(公告)号：US09324707B2

公开(公告)日：2016-04-26

申请号：US14323914

申请日：2014-07-03

Applicant: Infineon Technologies AG

Inventor： Henning Haffner ,  Manfred Eller ,  Richard Lindsay

IPC: H01L27/082 ,  H01L21/28 ,  H01L27/02 ,  G03F1/00 ,  G06F17/50 ,  H01L27/085 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F2217/12 ,  H01L21/0334 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/082 ,  H01L27/085 ,  H01L27/088 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T29/41

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract translation: 公开了集成电路及其制造和设计方法。 例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。 第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。 基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。 该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

公开(公告)号：US20140353757A1

公开(公告)日：2014-12-04

申请号：US14323914

申请日：2014-07-03

Applicant: Infineon Technologies AG

Inventor： Henning Haffner ,  Manfred Eller ,  Richard Lindsay

IPC: H01L27/082 ,  G06F17/50 ,  G03F1/00 ,  H01L27/085

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F2217/12 ,  H01L21/0334 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/082 ,  H01L27/085 ,  H01L27/088 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T29/41

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract translation: 公开了集成电路及其制造和设计方法。 例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。 第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。 基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。 该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

公开(公告)号：US09917191B2

公开(公告)日：2018-03-13

申请号：US14935067

申请日：2015-11-06

Applicant: Infineon Technologies AG

Inventor： Manfred Eller ,  Jin-Ping Han

IPC: H01L33/00 ,  H01L21/332 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

公开(公告)号：US20160283635A1

公开(公告)日：2016-09-29

申请号：US15093646

申请日：2016-04-07

Applicant: Infineon Technologies AG

Inventor： Henning Haffner ,  Manfred Eller ,  Richard Lindsay

IPC: G06F17/50 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F2217/12 ,  H01L21/0334 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/082 ,  H01L27/085 ,  H01L27/088 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T29/41

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

公开(公告)号：US20160064564A1

公开(公告)日：2016-03-03

申请号：US14935067

申请日：2015-11-06

Applicant: Infineon Technologies AG

Inventor： Manfred Eller ,  Jin-Ping Han

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.