公开(公告)号：US09087919B2

公开(公告)日：2015-07-21

申请号：US14251193

申请日：2014-04-11

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的衬底上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在衬底的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在衬底的第一区域中形成第一晶体管，该第一晶体管包括CMOS器件的NMOS FET，而衬底的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US10566426B2

公开(公告)日：2020-02-18

申请号：US15848707

申请日：2017-12-20

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Oliver Hellmund ,  Peter Irsigler ,  Jens Peter Konrath ,  David Laforet ,  Maik Langner ,  Markus Neuber ,  Hans-Joachim Schulze ,  Ralf Siemieniec ,  Knut Stahrenberg ,  Olaf Storbeck

IPC: H01L21/02 ,  H01L29/16 ,  H01L21/28 ,  H01L29/51

Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.

公开(公告)号：US20130224942A1

公开(公告)日：2013-08-29

申请号：US13854258

申请日：2013-04-01

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在工件的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在工件的第一区域中形成第一晶体管，其包括CMOS器件的NMOS FET，而在工件的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US09659778B2

公开(公告)日：2017-05-23

申请号：US14744781

申请日：2015-06-19

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

公开(公告)号：US09136187B2

公开(公告)日：2015-09-15

申请号：US13940545

申请日：2013-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  INFINEON TECHNOLOGIES AG

Inventor： Cheong Sik Yu ,  Choelhwyi Bae ,  JaeHoo Park ,  Knut Stahrenberg

IPC: H01L21/00 ,  H01L21/66

CPC classification number: H01L22/14 ,  H01L21/823412 ,  H01L22/12 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/1104

Abstract: A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate, monitoring processes of forming the first and second transistors to find an error and performing an additional ion implantation process to form a low-concentration dopant region or a halo region on the first transistor or the second transistor corresponding to a found error.

Abstract translation: 一种形成半导体器件的方法包括在衬底上形成第一晶体管和第二晶体管，监测形成第一和第二晶体管的过程，以发现误差并执行额外的离子注入工艺以形成低浓度掺杂剂区域或 第一晶体管或第二晶体管上的晕圈区域对应于发现的误差。

公开(公告)号：US20150364328A1

公开(公告)日：2015-12-17

申请号：US14744781

申请日：2015-06-19

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的衬底上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在衬底的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在衬底的第一区域中形成第一晶体管，该第一晶体管包括CMOS器件的NMOS FET，而衬底的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US20150017746A1

公开(公告)日：2015-01-15

申请号：US13940545

申请日：2013-07-12

Applicant: INFINEON TECHNOLOGIES AG ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheong Sik Yu ,  Choelhwyi Bae ,  JaeHoo Park ,  Knut Stahrenberg

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/823412 ,  H01L22/12 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/1104

Abstract: A method of forming a semiconductor device includes forming a first transistor and a second transistor on a substrate, monitoring processes of forming the first and second transistors to find an error and performing an additional ion implantation process to form a low-concentration dopant region or a halo region on the first transistor or the second transistor corresponding to a found error.

Abstract translation: 一种形成半导体器件的方法包括在衬底上形成第一晶体管和第二晶体管，监测形成第一和第二晶体管的过程，以发现误差并执行额外的离子注入工艺以形成低浓度掺杂剂区域或 第一晶体管或第二晶体管上的晕圈区域对应于发现的误差。

公开(公告)号：US20140220770A1

公开(公告)日：2014-08-07

申请号：US14251193

申请日：2014-04-11

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/8238 ,  H01L29/40

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的衬底上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在衬底的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在衬底的第一区域中形成第一晶体管，该第一晶体管包括CMOS器件的NMOS FET，而衬底的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。

公开(公告)号：US08778765B2

公开(公告)日：2014-07-15

申请号：US13854258

申请日：2013-04-01

Applicant: Infineon Technologies AG

Inventor： Knut Stahrenberg ,  Jin-Ping Han

IPC: H01L21/00

CPC classification number: H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Abstract translation: 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。 栅极材料堆叠包括半导体栅极材料。 在工件的第一区域或第二区域中改变厚度或将物质引入半导体栅极材料。 栅极材料堆叠在第一区域中被图案化，而第二区域在工件的第一区域中形成第一晶体管，其包括CMOS器件的NMOS FET，而在工件的第二区域中的第二晶体管包括NMOS FET CMOS器件。 第一晶体管具有第一阈值电压，而第二晶体管具有不同于第一阈值电压的第二阈值电压。