公开(公告)号：US20180210852A1

公开(公告)日：2018-07-26

申请号：US15924934

申请日：2018-03-19

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Schepers ,  Frank Hellwig

IPC: G06F13/364 ,  G06F13/40 ,  G06F13/42 ,  G06F15/78 ,  G06F13/24

CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7807

Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

公开(公告)号：US09946674B2

公开(公告)日：2018-04-17

申请号：US15140815

申请日：2016-04-28

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Schepers ,  Frank Hellwig

IPC: G06F12/06 ,  G06F13/364 ,  G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7807

Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

公开(公告)号：US10061729B2

公开(公告)日：2018-08-28

申请号：US15924934

申请日：2018-03-19

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Schepers ,  Frank Hellwig

IPC: G06F13/38 ,  G06F13/364 ,  G06F13/40 ,  G06F13/24 ,  G06F15/78 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7807

Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

公开(公告)号：US20170315944A1

公开(公告)日：2017-11-02

申请号：US15140815

申请日：2016-04-28

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Joerg Schepers ,  Frank Hellwig

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F15/78 ,  G06F13/24

CPC classification number: G06F13/364 ,  G06F13/24 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7807

Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.