公开(公告)号：US09741639B2

公开(公告)日：2017-08-22

申请号：US14027603

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Frank Umbach ,  Niels Oeschler ,  Kirill Trunov

IPC: H01L23/48 ,  H01L21/336 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L23/48 ,  H01L21/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/2908 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1≧1 or N1≧2 of first partial layers and a number N2≧2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.

公开(公告)号：US20240047439A1

公开(公告)日：2024-02-08

申请号：US18368914

申请日：2023-09-15

Applicant: Infineon Technologies AG

Inventor： Kirill Trunov ,  Waltraud Eisenbeil ,  Frederick Groepper ,  Joerg Schadewald ,  Arthur Unrau ,  Ulrich Wilke

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32227 ,  H01L2224/32507 ,  H01L2224/8381 ,  H01L2224/83815

Abstract: An electronic device includes a substrate including first and second metal regions, a first passive device that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the first passive device facing first metal region, a semiconductor die that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the semiconductor die facing the second metal region, a first soldered joint between the metal joining surface of the first passive device and the first metal region; and a second soldered joint between the metal joining surface of the semiconductor die and the second metal region, wherein a minimum thickness of the first soldered joint is greater than a maximum thickness of the second soldered joint.

公开(公告)号：US11798924B2

公开(公告)日：2023-10-24

申请号：US16902725

申请日：2020-06-16

Applicant: Infineon Technologies AG

Inventor： Kirill Trunov ,  Waltraud Eisenbeil ,  Frederick Groepper ,  Joerg Schadewald ,  Arthur Unrau ,  Ulrich Wilke

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L25/16 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32227 ,  H01L2224/32507 ,  H01L2224/8381 ,  H01L2224/83815

Abstract: A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.

公开(公告)号：US20210391310A1

公开(公告)日：2021-12-16

申请号：US16902725

申请日：2020-06-16

Applicant: Infineon Technologies AG

Inventor： Kirill Trunov ,  Waltraud Eisenbeil ,  Frederick Groepper ,  Joerg Schadewald ,  Arthur Unrau ,  Ulrich Wilke

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.

公开(公告)号：US20140077376A1

公开(公告)日：2014-03-20

申请号：US14027603

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Frank Umbach ,  Niels Oeschler ,  Kirill Trunov

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/48 ,  H01L21/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/2908 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1≧1 or N1≧2 of first partial layers and a number N2≧2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.

Abstract translation: 半导体芯片包括半导体本体和施加在半导体本体上的芯片金属化。 芯片金属化具有背向半导体本体的底面。 芯片还包括施加到芯片金属化的下侧的层叠体，并且具有第一部分层的数量N1≥1或N1≥2以及第二部分层的数量N2≥2。 第一部分层和第二部分层被交替且相继地布置，使得第二部分层中的至少一个布置在每个第一对第一部分层的第一部分层之间，并且使得第一部分层和第二部分层中的至少一个 每层第二部分层的第二部分层之间布置有层。