公开(公告)号：US20230326820A1

公开(公告)日：2023-10-12

申请号：US17715108

申请日：2022-04-07

Applicant: Infineon Technologies AG

Inventor： Johannes Uhlig ,  Ulrich Wilke

IPC: H01L23/29 ,  H01L23/31

CPC classification number: H01L23/293 ,  H01L23/291 ,  H01L23/3107 ,  H02M7/003

Abstract: A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a volume of electrically insulating polymer material disposed within the interior volume, and a concentration of sacrificial particles dispersed within the volume of electrically insulating polymer, wherein the sacrificial particles are a metal salt, semi-metal salt, metal oxide, or semi-metal oxide with a cation.

公开(公告)号：US20210398821A1

公开(公告)日：2021-12-23

申请号：US17342975

申请日：2021-06-09

Applicant: Infineon Technologies AG

Inventor： Fabian Craes ,  Carsten Ehlers ,  Olaf Hohlfeld ,  Ulrich Wilke

IPC: H01L21/54 ,  H01L21/48 ,  H01L21/56 ,  H01L21/308 ,  H01L21/67 ,  H01L23/00

Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.

公开(公告)号：US11715647B2

公开(公告)日：2023-08-01

申请号：US17342975

申请日：2021-06-09

Applicant: Infineon Technologies AG

Inventor： Fabian Craes ,  Carsten Ehlers ,  Olaf Hohlfeld ,  Ulrich Wilke

IPC: H01L21/54 ,  H01L21/48 ,  H01L21/308 ,  H01L21/56 ,  H01L21/67 ,  H01L23/00

CPC classification number: H01L21/54 ,  H01L21/308 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/67069 ,  H01L24/27

Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.

公开(公告)号：US20210305062A1

公开(公告)日：2021-09-30

申请号：US17202849

申请日：2021-03-16

Applicant: Infineon Technologies AG

Inventor： Charles Rimbert-Riviere ,  Martin Goldammer ,  Lydia Lottspeich ,  Ulrich Wilke

IPC: H01L21/48 ,  H01L23/498

Abstract: A method for forming a semiconductor substrate arrangement includes: forming a mask on a semiconductor substrate, the semiconductor substrate including and a metallization layer arranged on an insulation layer, the metallization layer arranged between the mask and insulation layer; forming a layer of electrically conductive coating on the metallization layer, the electrically conductive coating formed in at least one opening of the mask on regions of the metallization layer that are not covered by the mask; and after forming the electrically conductive coating, removing the mask. Forming the mask includes either applying an even layer of material on the metallization layer, or applying the material of the mask on the metallization layer such that the thickness of the mask in a region adjacent to edges of the mask is greater than the thickness of the regions of the mask further away from the edges.

公开(公告)号：US20250062175A1

公开(公告)日：2025-02-20

申请号：US18802475

申请日：2024-08-13

Applicant: Infineon Technologies AG

Inventor： Charles Rimbert-Riviere ,  Georg Troska ,  Lydia Lottspeich ,  Martin Goldammer ,  Ulrich Wilke ,  Benedikt Domes ,  Lars Böwer

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L25/07

Abstract: A method for producing a substrate for a semiconductor module includes: forming a first electrically conductive layer on a first side of a dielectric insulation layer; structuring the first electrically conductive layer by creating one or more incisions through the first electrically conductive layer that extend from an upper surface of the first electrically conductive layer down to the dielectric insulation layer, thereby completely separating different sections of the first electrically conductive layer; and forming a passivation layer covering the entire upper surface of the structured first electrically conductive layer.

公开(公告)号：US12205826B2

公开(公告)日：2025-01-21

申请号：US17202849

申请日：2021-03-16

Applicant: Infineon Technologies AG

Inventor： Charles Rimbert-Riviere ,  Martin Goldammer ,  Lydia Lottspeich ,  Ulrich Wilke

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A method for forming a semiconductor substrate arrangement includes: forming a mask on a semiconductor substrate, the semiconductor substrate including and a metallization layer arranged on an insulation layer, the metallization layer arranged between the mask and insulation layer; forming a layer of electrically conductive coating on the metallization layer, the electrically conductive coating formed in at least one opening of the mask on regions of the metallization layer that are not covered by the mask; and after forming the electrically conductive coating, removing the mask. Forming the mask includes either applying an even layer of material on the metallization layer, or applying the material of the mask on the metallization layer such that the thickness of the mask in a region adjacent to edges of the mask is greater than the thickness of the regions of the mask further away from the edges.

公开(公告)号：US20240047439A1

公开(公告)日：2024-02-08

申请号：US18368914

申请日：2023-09-15

Applicant: Infineon Technologies AG

Inventor： Kirill Trunov ,  Waltraud Eisenbeil ,  Frederick Groepper ,  Joerg Schadewald ,  Arthur Unrau ,  Ulrich Wilke

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32227 ,  H01L2224/32507 ,  H01L2224/8381 ,  H01L2224/83815

Abstract: An electronic device includes a substrate including first and second metal regions, a first passive device that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the first passive device facing first metal region, a semiconductor die that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the semiconductor die facing the second metal region, a first soldered joint between the metal joining surface of the first passive device and the first metal region; and a second soldered joint between the metal joining surface of the semiconductor die and the second metal region, wherein a minimum thickness of the first soldered joint is greater than a maximum thickness of the second soldered joint.

公开(公告)号：US11798924B2

公开(公告)日：2023-10-24

申请号：US16902725

申请日：2020-06-16

Applicant: Infineon Technologies AG

Inventor： Kirill Trunov ,  Waltraud Eisenbeil ,  Frederick Groepper ,  Joerg Schadewald ,  Arthur Unrau ,  Ulrich Wilke

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L25/16 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32227 ,  H01L2224/32507 ,  H01L2224/8381 ,  H01L2224/83815

Abstract: A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.

公开(公告)号：US20230063856A1

公开(公告)日：2023-03-02

申请号：US17899541

申请日：2022-08-30

Applicant: Infineon Technologies AG

Inventor： Oliver Schilling ,  Roman Immel ,  Joachim Seifert ,  Altan Toprak ,  Frank Wagner ,  Ulrich Wilke ,  Lars Boewer ,  Paul Frank

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor die including a first side and an opposing second side, a first metallization layer arranged on the first side, a Ni including layer arranged on the second side, wherein the Ni including layer further includes one or more of Si, Cr and Ti, and a SnSb layer arranged on the Ni comprising layer, wherein an amount of Sb in the SnSb layer is in the range of 2 wt % to 30 wt %.

公开(公告)号：US20210391310A1

公开(公告)日：2021-12-16

申请号：US16902725

申请日：2020-06-16

Applicant: Infineon Technologies AG

Inventor： Kirill Trunov ,  Waltraud Eisenbeil ,  Frederick Groepper ,  Joerg Schadewald ,  Arthur Unrau ,  Ulrich Wilke

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.