公开(公告)号：US20220310536A1

公开(公告)日：2022-09-29

申请号：US17699666

申请日：2022-03-21

Applicant: Infineon Technologies AG

Inventor： Johannes Uhlig ,  Jens Krugmann ,  Ulrich Nolten ,  Regina Nottelmann ,  Arthur Unrau

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/49 ,  H01L21/48 ,  H01L25/07

Abstract: A housing for a power semiconductor module arrangement includes sidewalls and a lid. The lid includes a first layer of a first material having a plurality of openings, and second layer of a second material that is different from the first material. The second layer completely covers a bottom surface of the first layer. The second layer includes a plurality of protrusions, each protrusion extending into a different one of the plurality of openings of the first layer such that each of the plurality of openings is completely covered by one of the protrusions.

公开(公告)号：US20210242111A1

公开(公告)日：2021-08-05

申请号：US17160612

申请日：2021-01-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Carsten Ehlers ,  Arthur Unrau

IPC: H01L23/49 ,  H01L23/31 ,  H01L23/14 ,  H01L23/492 ,  H01L23/08 ,  H01L23/00 ,  H01L21/48

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

公开(公告)号：US11942335B2

公开(公告)日：2024-03-26

申请号：US17989196

申请日：2022-11-17

Applicant: Infineon Technologies AG

Inventor： Achim Muecke ,  Arthur Unrau

IPC: H01L21/48 ,  H01L23/492 ,  H01L25/00 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L21/4871 ,  H01L23/4922 ,  H01L25/50 ,  H01L25/072 ,  H01L25/18

Abstract: A method of manufacturing a module is disclosed. In one example, the method comprises providing at least one solder body with a base portion and an elevated edge extending along at least part of a circumference of the base portion. At least one carrier, on which at least one electronic component is mounted, is placed in the at least one solder body so that the at least one carrier is positioned on the base portion and is spatially confined by the elevated edge.

公开(公告)号：US20230369175A1

公开(公告)日：2023-11-16

申请号：US18144464

申请日：2023-05-08

Applicant: Infineon Technologies AG

Inventor： Arthur Unrau ,  Matthias Droste ,  Achim Mücke

IPC: H01L23/492 ,  H01L23/049 ,  H01L23/31 ,  H01L25/07 ,  H01L21/48

CPC classification number: H01L23/492 ,  H01L23/049 ,  H01L23/3107 ,  H01L25/072 ,  H01L21/4875

Abstract: A power semiconductor module arrangement includes: a base plate; substrates arranged on a first surface of the base plate; a connection layer arranged between a different one of the substrates and the base plate and permanently attaching the respective substrate to the base plate; and a spacer arranged between one of the substrates and the base plate and embedded in a material of the respective connection layer. For at least one substrate: either no spacer or one or more of a first kind of spacers having a first height in a vertical direction perpendicular to the first surface of the base plate is arranged below a first half of the respective substrate, and one or more of a second kind of spacers having a second height in the vertical direction is arranged below a second half of the respective substrate, the second height being greater than the first height.

公开(公告)号：US12148718B2

公开(公告)日：2024-11-19

申请号：US17699666

申请日：2022-03-21

Applicant: Infineon Technologies AG

Inventor： Johannes Uhlig ,  Jens Krugmann ,  Ulrich Nolten ,  Regina Nottelmann ,  Arthur Unrau

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/053 ,  H01L23/49 ,  H01L25/07 ,  H01L23/24 ,  H01L23/31

Abstract: A housing for a power semiconductor module arrangement includes sidewalls and a lid. The lid includes a first layer of a first material having a plurality of openings, and second layer of a second material that is different from the first material. The second layer completely covers a bottom surface of the first layer. The second layer includes a plurality of protrusions, each protrusion extending into a different one of the plurality of openings of the first layer such that each of the plurality of openings is completely covered by one of the protrusions.

公开(公告)号：US20240429181A1

公开(公告)日：2024-12-26

申请号：US18823796

申请日：2024-09-04

Applicant: Infineon Technologies AG

Inventor： Johannes Uhlig ,  Jens Krugmann ,  Ulrich Nolten ,  Regina Nottelmann ,  Arthur Unrau

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/053 ,  H01L23/24 ,  H01L23/31 ,  H01L23/49 ,  H01L25/07

Abstract: A method for forming a lid of a housing includes: forming a first layer of a first material having a plurality of openings; forming a second layer of a second material that is different from the first material, the second layer having a plurality of protrusions; and arranging the second layer on the first layer such that the second layer completely covers a bottom surface of the first layer, and each protrusion extends into a different one of the plurality of openings of the first layer such that each of the plurality of openings is completely covered by one of the protrusions.

公开(公告)号：US11935811B2

公开(公告)日：2024-03-19

申请号：US17403298

申请日：2021-08-16

Applicant: Infineon Technologies AG

Inventor： Arthur Unrau ,  Elmar Kuehle

IPC: H01L23/373 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/3735 ,  H01L23/53223 ,  H01L29/1608

Abstract: A baseplate for a semiconductor module comprises at least one elevation. The at least one elevation is formed integrally with the baseplate. The baseplate has a uniform first thickness or a thickness which decreases continuously from the edge regions toward the center and which is increased locally up to a maximum second thickness in the region of each of the at least one elevation.

公开(公告)号：US20230170286A1

公开(公告)日：2023-06-01

申请号：US18070092

申请日：2022-11-28

Applicant: Infineon Technologies AG

Inventor： Arthur Unrau ,  Florian Dreps ,  Christoph Koch ,  Till Neddermann ,  Christian Steininger

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/07 ,  H01L25/18 ,  H01L23/053 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L23/5383 ,  H01L25/072 ,  H01L25/18 ,  H01L23/053 ,  H01L21/4842 ,  H01L24/73

Abstract: A terminal element or bus bar for a power semiconductor module arrangement includes a first end configured to be arranged inside a housing of the power semiconductor module arrangement, a second end configured to be arranged outside of the housing of the power semiconductor module arrangement, and at least a first section and a second section arranged successively between the first end and the second end along a length of the terminal element or bus bar, wherein either the first section includes a first material, the second section includes a second material, and the first material differs from the second material, or the first section has a first thickness, the second section has a second thickness, and the first thickness differs from the second thickness, or both.

公开(公告)号：US12272669B2

公开(公告)日：2025-04-08

申请号：US17582832

申请日：2022-01-24

Applicant: Infineon Technologies AG

Inventor： Arthur Unrau ,  Szabolcs Barna ,  Tobias Buehner ,  Norbert Kanvasi

IPC: B23K1/00 ,  B23K3/08 ,  H01L23/00 ,  B23K101/40

Abstract: An arrangement includes a chamber, a heating element arranged in the chamber, wherein the heating element, when a first connection partner with a pre-connection layer formed thereon is arranged in the chamber, is configured to heat the first connection partner and the pre-connection layer, thereby melting the pre-connection layer, and a cooling trap. During the process of heating the first connection partner with the pre-connection layer formed thereon, the cooling trap has a temperature that is lower than the temperature of all other components of or in the chamber such that liquid evaporating from the pre-connection layer is attracted by and condenses on the cooling trap.

公开(公告)号：US20240047439A1

公开(公告)日：2024-02-08

申请号：US18368914

申请日：2023-09-15

Applicant: Infineon Technologies AG

Inventor： Kirill Trunov ,  Waltraud Eisenbeil ,  Frederick Groepper ,  Joerg Schadewald ,  Arthur Unrau ,  Ulrich Wilke

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32227 ,  H01L2224/32507 ,  H01L2224/8381 ,  H01L2224/83815

Abstract: An electronic device includes a substrate including first and second metal regions, a first passive device that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the first passive device facing first metal region, a semiconductor die that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the semiconductor die facing the second metal region, a first soldered joint between the metal joining surface of the first passive device and the first metal region; and a second soldered joint between the metal joining surface of the semiconductor die and the second metal region, wherein a minimum thickness of the first soldered joint is greater than a maximum thickness of the second soldered joint.