公开(公告)号：US20180190620A1

公开(公告)日：2018-07-05

申请号：US15905086

申请日：2018-02-26

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

摘要： Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

公开(公告)号：US20180158797A1

公开(公告)日：2018-06-07

申请号：US15869673

申请日：2018-01-12

申请人： International Business Machines Corporation

发明人： Charles L. Arvin ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/00 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L24/81 ,  B23K35/025 ,  B23K35/262 ,  B23K35/302 ,  B23K35/3033 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13211 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13447 ,  H01L2224/13455 ,  H01L2224/13541 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/17505 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/8112 ,  H01L2224/81193 ,  H01L2224/81211 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/00012

摘要： A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

公开(公告)号：US09847310B2

公开(公告)日：2017-12-19

申请号：US14812861

申请日：2015-07-29

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. Seddon ,  Francis J. Carney

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L24/17 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13294 ,  H01L2224/13311 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81211 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/81

摘要： A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The newly formed alloy has a higher melting temperature than the first reflow temperature. Accordingly, additional die may be reflowed and attached to the board without causing the bonding of the first die to the board to fail if the same reflow temperature is used.

公开(公告)号：US20170301641A1

公开(公告)日：2017-10-19

申请号：US15640997

申请日：2017-07-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Ming Chen ,  Cheng-Hsien Hsieh ,  Sung-Hui Huang ,  Kuo-Ching Hsu

IPC分类号： H01L23/00 ,  H01L23/538 ,  B23K1/00 ,  H01L25/065 ,  H01L25/00 ,  B23K101/40

CPC分类号： H01L24/16 ,  B23K1/0016 ,  B23K2101/40 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/16145 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/81

摘要： A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

公开(公告)号：US20170179071A1

公开(公告)日：2017-06-22

申请号：US15244069

申请日：2016-08-23

申请人： International Business Machines Corporation

发明人： Charles L. Arvin ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/00 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L24/81 ,  B23K35/025 ,  B23K35/262 ,  B23K35/302 ,  B23K35/3033 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13211 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13447 ,  H01L2224/13455 ,  H01L2224/13541 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/17505 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/8112 ,  H01L2224/81193 ,  H01L2224/81211 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/00012

摘要： A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

公开(公告)号：US09679875B2

公开(公告)日：2017-06-13

申请号：US15135599

申请日：2016-04-22

申请人： International Business Machines Corporation

发明人： Peter A. Gruber ,  Katsuyuki Sakuma ,  Da-Yuan Shih

IPC分类号： H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0612 ,  H01L2224/065 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/1141 ,  H01L2224/1144 ,  H01L2224/11849 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2224/16012 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81022 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81201 ,  H01L2224/8121 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/01047 ,  H01L2924/01029

摘要： A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

公开(公告)号：US09653423B2

公开(公告)日：2017-05-16

申请号：US15079335

申请日：2016-03-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/81 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/15311 ,  H01L2924/3656 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

摘要： An embodiment is an integrated circuit structure including a first die having a bump structure, and a second die having a pad structure. The first die is attached to the second die by bonding the bump structure and the pad structure. The bump structure includes a metal pillar, a metal cap layer on the metal pillar, a metal insertion layer on the metal cap layer, and a solder layer on the metal insertion layer. The pad structure includes at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer.

公开(公告)号：US09601374B2

公开(公告)日：2017-03-21

申请号：US14669780

申请日：2015-03-26

申请人： Micron Technology, Inc.

发明人： Owen R. Fay ,  Liana Foster

IPC分类号： H01L25/065 ,  H01L21/78 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L21/78 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/29294 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81211 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/8385 ,  H01L2224/85051 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/8581 ,  H01L2224/85815 ,  H01L2224/85951 ,  H01L2224/92147 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2924/00

摘要： A semiconductor die assembly having a solderball wirebonded to a substrate. As an example, the semiconductor die assembly may include the solderball attached to a bond pad on a face surface of a memory die. A non-face surface of the memory die can be attached to the substrate. A wire can be wirebonded to the solderball at a first end of the wire and connected to the substrate at a second end of the wire.

公开(公告)号：US20170033067A1

公开(公告)日：2017-02-02

申请号：US14809296

申请日：2015-07-27

申请人： Infineon Technologies AG

发明人： Stefan Kramp

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/06 ,  H01L21/76832 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13118 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45157 ,  H01L2224/48245 ,  H01L2224/48491 ,  H01L2224/73207 ,  H01L2224/8181 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/0361 ,  H01L2924/01074

摘要： According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

摘要翻译： 根据各种实施例，半导体器件可以包括：在半导体器件的正面上的至少一个第一接触焊盘; 在所述半导体器件的正面上的至少一个第二接触焊盘; 至少部分地布置在所述至少一个第一接触垫上的层堆叠，其中所述至少一个第二接触焊盘至少部分地不含所述层堆叠; 其中所述层堆叠至少包括粘附层和金属化层; 并且其中所述金属化层包括金属合金，并且其中所述粘合层设置在所述金属化层和所述至少一个第一接触焊盘之间，用于将所述金属化层的所述金属合金粘附到所述至少一个第一接触焊盘。

公开(公告)号：US20160358875A1

公开(公告)日：2016-12-08

申请号：US15239745

申请日：2016-08-17

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Yu-Hsiang HSIAO ,  Chiu-Wen LEE ,  Ping-Feng YANG ,  Kwang-Lung LIN

IPC分类号： H01L23/00 ,  H01L25/00 ,  C22C9/02 ,  B23K35/26 ,  B23K1/00 ,  C22C13/00 ,  H01L25/065 ,  B23K35/30

CPC分类号： H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

摘要翻译： 半导体器件包括第一电路层，邻近第一电路层设置的铜柱，第二电路层和焊料层。 第二电路层包括电接触和设置在电接触上的表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。 焊料层设置在铜柱和表面光洁剂层之间。 焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的两种或更多种的组合，第二IMC包括金和锡的组合，钯的组合 和锡，或两者。